Abstract: A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a doped region of the semiconductor substrate. A gate terminal of the depletion mode transistor is formed over at least a portion of the doped region as a field plate that is switchably connectable to a source terminal of the source-down enhancement mode transistor. A control circuit may be provided to facilitate a connection between the gate terminal of the depletion mode transistor and the source terminal of the source-down enhancement mode transistor when the power MOSFET integrated circuit is in an OFF state. The control circuit may also be configured to facilitate connection of the gate terminal of the depletion mode transistor to a gate terminal of the source-down enhancement mode FET device or to an external driver that provides a reference voltage, when the power MOSFET is in an ON state.

Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.

Abstract: A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.

Abstract: A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

Abstract: A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a doped region of the semiconductor substrate. A gate terminal of the depletion mode transistor is formed over at least a portion of the doped region as a field plate that is switchably connectable to a source terminal of the source-down enhancement mode transistor. A control circuit may be provided to facilitate a connection between the gate terminal of the depletion mode transistor and the source terminal of the source-down enhancement mode transistor when the power MOSFET integrated circuit is in an OFF state. The control circuit may also be configured to facilitate connection of the gate terminal of the depletion mode transistor to a gate terminal of the source-down enhancement mode FET device or to an external driver that provides a reference voltage, when the power MOSFET is in an ON state.

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

Abstract: An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused metal oxide semiconductor (LDMOS) transistor and a low side transistor formed on the chip and comprising a source down metal oxide semiconductor field effect transistor (MOSFET). The chip also includes a substrate of the chip for use as a source for the low side transistor and an n-doped well for isolation of the high side transistor from the source of the low side transistor.

Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad. The device further comprises an intermetallic compound interface located between the bond pad and the wire and a silicon nitride or silicon carbonyl layer covering the intermetallic compound interface.

Abstract: An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused metal oxide semiconductor (LDMOS) transistor and a low side transistor formed on the chip and comprising a source down metal oxide semiconductor field effect transistor (MOSFET). The chip also includes a substrate of the chip for use as a source for the low side transistor and an n-doped well for isolation of the high side transistor from the source of the low side transistor.

Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad.