Patents by Inventor Frank A. Walian

Frank A. Walian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for fixing best case hold time violations in an integrated circuit design
    Patent number: 7590957
    Abstract: The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to the hold violation, from an end point of the path toward a start point of the path, until an element is reached that corresponds to the start point or has a fanout exceeding a predetermined fanout limit. The method and apparatus then generate an output that defines a location in the design at which to insert a delay element, such that the delay element is connected to an input of an element downstream of the element reached during tracing.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: September 15, 2009
    Assignee: LSI Corporation
    Inventors: Frank A. Walian, John S-H Kim
  • Method and apparatus for fixing best case hold time violations in an integrated circuit design
    Publication number: 20080052652
    Abstract: The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to the hold violation, from an end point of the path toward a start point of the path, until an element is reached that corresponds to the start point or has a fanout exceeding a predetermined fanout limit. The method and apparatus then generate an output that defines a location in the design at which to insert a delay element, such that the delay element is connected to an input of an element downstream of the element reached during tracing.
    Type: Application
    Filed: August 24, 2006
    Publication date: February 28, 2008
    Applicant: LSI Logic Corporation
    Inventors: Frank A. Walian, John S-H Kim
  • Gate reuse methodology for diffused cell-based IP blocks in platform-based silicon products
    Patent number: 7062739
    Abstract: A method for re-using diffused cell-based IP blocks in a structured application specific integrated circuit comprising the steps of (A) implementing one or more blocks of intellectual property (IP) using a plurality of cell-based building blocks and (B) providing one or more alternative views for at least one of the one or more blocks of intellectual property.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: June 13, 2006
    Assignee: LSI Logic Corporation
    Inventors: James G. Monthie, Frank A. Walian, Samit K. Chakraborty
  • Gate reuse methodology for diffused cell-based IP blocks in platform-based silicon products
    Publication number: 20050097493
    Abstract: A method for re-using diffused cell-based IP blocks in a structured application specific integrated circuit comprising the steps of (A) implementing one or more blocks of intellectual property (IP) using a plurality of cell-based building blocks and (B) providing one or more alternative views for at least one of the one or more blocks of intellectual property.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 5, 2005
    Inventors: James Monthie, Frank Walian, Samit Chakraborty