Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: An equalizer, for providing a tunable pole/zero compensated output signal, includes a integrated tone control circuit with a MOSFET-C configuration such that the spacing between the pole and the zero and the center frequency of the pole/zero pair can be tuned by varying the resistance of MOSFET resistors using variable voltage sources applied to the gates of the MOSFETs.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: An amplifier for providing a pole/zero compensated output signal by generating multiple pole/zero pairs at predetermined increasing frequencies, with the number of pole/zero pairs occurring at the increasing frequencies increasing geometrically. The amplifier includes three amplifier circuits cascaded in series to generate a first pole/zero pair at a predetermined frequency, and a second and a third pole/zero pair both generated at a second frequency two octaves above the first pole/zero pair. The first amplifier circuit configured to generate the first pole/zero pair and the second and third amplifier circuits each configured to generate the second and third pole/zero pairs. The relative spacing between each pole and its corresponding zero determines the amount of compensation performed.

Abstract: An interface for current mode to Manchester encoded serial signals includes symmetric positive/negative doublet pulse generation. The doublet pulse generator provides a pulse duration held constant by feedback and a voltage/current reference and a minimal gap between the positive and negative polarity pulses by using the same signal to both turn off the positive pulse driver and turn on the negative pulse driver. Fault detection by sensing of asymmetry in received pulse uses a comparator with both high and low threshold input devices to provide minor asymmetry tolerance.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: A communications receiver, wherein an elastic store FIFO buffers clock-phase jitter. A jitter estimate is obtained by a very simple circuit, wherein the read clock is used as a reference to sample the FIFO address pointers.