Patents by Inventor Frank B. Parrish

Frank B. Parrish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9786977
    Abstract: An example circuit board structure includes: a substrate; and vias that are electrically conductive and that pass through the substrate to enable electrical connection through the circuit board structure. The substrate is thinner, and lengths of the vias are shorter, in first areas of the circuit board structure that deliver first speed signals than in second areas of the circuit board structure that deliver second speed signals and power. The first speed signals have a shorter rise time than the second speed signals.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 10, 2017
    Assignee: Teradyne, Inc.
    Inventors: Timothy Daniel Lyons, Frank B. Parrish, Roger Allen Sinsheimer, Brian G. Donovan, Vladimir Vayner, Brandon E. Creager, Brian C. Wadell
  • Publication number: 20170170537
    Abstract: An example circuit board structure includes: a substrate; and vias that are electrically conductive and that pass through the substrate to enable electrical connection through the circuit board structure. The substrate is thinner, and lengths of the vias are shorter, in first areas of the circuit board structure that deliver first speed signals than in second areas of the circuit board structure that deliver second speed signals and power. The first speed signals have a shorter rise time than the second speed signals.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 15, 2017
    Inventors: Timothy Daniel Lyons, Frank B. Parrish, Roger Allen Sinsheimer, Brian G. Donovan, Vladimir Vayner, Brandon E. Creager, Brian C. Wadell
  • Patent number: 8622752
    Abstract: Apparatus and methods for fabricating an interposer that may be used in testing a large number of electronic circuits or devices in parallel. The interposer may be fabricated from a plurality of modules that may be assembled into a selected shape, such that the assembled modules substantially fill the selected shape, e.g., a circle approximately the size of a semiconductor wafer. The plurality of modules may be formed from a single base shape (e.g., formed from a single injection mold). A portion of the formed modules may be machined into a first machined shape, or first and second machined shapes. The assembled modules may include only the base shape and first machined shape or first and second machined shapes. The limited number of shapes can reduce fabrication costs for an interposer.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: January 7, 2014
    Assignee: Teradyne, Inc.
    Inventors: Frank B. Parrish, Josh M. Mellinger
  • Publication number: 20120264320
    Abstract: Apparatus and methods for fabricating an interposer that may be used in testing a large number of electronic circuits or devices in parallel. The interposer may be fabricated from a plurality of modules that may be assembled into a selected shape, such that the assembled modules substantially fill the selected shape, e.g., a circle approximately the size of a semiconductor wafer. The plurality of modules may be formed from a single base shape (e.g., formed from a single injection mold). A portion of the formed modules may be machined into a first machined shape, or first and second machined shapes. The assembled modules may include only the base shape and first machined shape or first and second machined shapes. The limited number of shapes can reduce fabrication costs for an interposer.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Applicant: Teradyne, Inc.
    Inventors: Frank B. Parrish, Josh M. Mellinger
  • Patent number: 8201328
    Abstract: In one implementation, a method is provided for constructing an interface module which includes constructing a board having a signal via through the board, and having at least one ground via extending through the board. The method further includes back drilling the signal via to create a center conductor hole above a remaining portion of the signal via and back drilling a shield opening in the board and at least part way into the at least one ground via such that a height of the center conductor hole is reduced. The method further includes plating the shield opening and the center conductor hole, and back drilling to remove a portion of the plating to electrically isolate the plated shield opening and the plated center conductor hole.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: June 19, 2012
    Assignee: Tyco Electronics Corporation
    Inventors: Roya Yaghmai, Frank B. Parrish, Daniel DeLessert
  • Patent number: 7977583
    Abstract: A shielded cable interface module having cable receiving grooves extending laterally to an edge of the board, each including a center conductor groove, an insulator groove, and a shield groove. A center conductor via and a shield via extend through the board. A conductor plane on the cable termination side surrounds the cable receiving grooves. The conductor plane includes a non-conductor region within the conductor plane adjacent to each of the conductor center conductor grooves. Ground vias associated with the cable receiving grooves are spaced apart from and partially surround the center conductor via outside and adjacent to the non-conductor region, the ground vias extend through the printed circuit board from the cable termination side to the system interface side.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: July 12, 2011
    Assignee: Teradyne, Inc.
    Inventors: Roya Yaghmai, Frank B. Parrish, Steven Hauptman
  • Patent number: 7815466
    Abstract: In one embodiment, an interface module is provided for connecting a plurality of signal paths to a high signal density interface. The interface module includes a board having axial conductor receptacles. The axial conductor receptacles have at least one ground via extending through the board to an interface side of the board and a shield receiving hole in the board extending into the board from a cable side of the board. At least a portion of the at least one ground via being exposed within the shield receiving hole, the shield receiving hole having a plating therein contacting the portion of the at least one ground via exposed within the shield receiving hole. The axial conductor receptacles have a plated center conductor receiving hole in the board, which extends to a signal via. The signal via extends from the center conductor hole to the interface side of the board. A non-plated hole in the board is located between the plated center conductor hole and the shield receiving hole.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: October 19, 2010
    Assignee: Teradyne, Inc.
    Inventors: Roya Yaghmai, Frank B. Parrish, Daniel DeLessert
  • Publication number: 20090258538
    Abstract: In one implementation, a method is provided for constructing an interface module which includes constructing a board having a signal via through the board, and having at least one ground via extending through the board. The method further includes back drilling the signal via to create a center conductor hole above a remaining portion of the signal via and back drilling a shield opening in the board and at least part way into the at least one ground via such that a height of the center conductor hole is reduced. The method further includes plating the shield opening and the center conductor hole, and back drilling to remove a portion of the plating to electrically isolate the plated shield opening and the plated center conductor hole.
    Type: Application
    Filed: December 4, 2008
    Publication date: October 15, 2009
    Inventors: Roya Yaghmai, Frank B. Parrish, Daniel DeLessert
  • Publication number: 20090176406
    Abstract: In one embodiment, an interface module is provided for connecting a plurality of signal paths to a high signal density interface. The interface module includes a board having axial conductor receptacles. The axial conductor receptacles have at least one ground via extending through the board to an interface side of the board and a shield receiving hole in the board extending into the board from a cable side of the board. At least a portion of the at least one ground via being exposed within the shield receiving hole, the shield receiving hole having a plating therein contacting the portion of the at least one ground via exposed within the shield receiving hole. The axial conductor receptacles have a plated center conductor receiving hole in the board, which extends to a signal via. The signal via extends from the center conductor hole to the interface side of the board. A non-plated hole in the board is located between the plated center conductor hole and the shield receiving hole.
    Type: Application
    Filed: December 4, 2008
    Publication date: July 9, 2009
    Inventors: Roya Yaghmai, Frank B. Parrish, Daniel DeLessert
  • Publication number: 20090151993
    Abstract: A shielded cable interface module having cable receiving grooves extending laterally to an edge of the board, each including a center conductor groove, an insulator groove, and a shield groove. A center conductor via and a shield via extend through the board. A conductor plane on the cable termination side surrounds the cable receiving grooves. The conductor plane includes a non-conductor region within the conductor plane adjacent to each of the conductor center conductor grooves. Ground vias associated with the cable receiving grooves are spaced apart from and partially surround the center conductor via outside and adjacent to the non-conductor region, the ground vias extend through the printed circuit board from the cable termination side to the system interface side.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 18, 2009
    Inventors: Roya Yaghmai, Frank B. Parrish, Steven Hauptman
  • Patent number: 7541819
    Abstract: The traditional device interface board is replaced by a number of smaller strips containing one or more electrical components for interfacing the device under test and the test head. The device interface modules may mount to a stiffening member having a back bone and multiple ribs running through the stiffening member. The device interface strips can create a lattice-like structure for the interface circuitry. Individual circuits may be disposed on the interface strips to perform functionality relating to the device under test and/or the test head.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: June 2, 2009
    Assignee: Teradyne, Inc.
    Inventors: Frank B. Parrish, Brian Brecht, Derek Castellano
  • Patent number: 7504822
    Abstract: A device for interfacing a test head and a prober is disclosed using wires or cables to provide the connection from a probe card interface boards to the probe card. The use of wires or cables, in place of the traditional pogo pin arrangement allows for more reliable and efficient testing, as well as additional high performance tests to be run. Optionally, a probe interface contains a stiffening member with multiple sidewalks and individual, configuration-specific probe card interface strips are connected to a probe card through zero insertion force clamps. The probe card interface attaches to the test head using standard probe interface board (“PIB”) docking mechanics. The assembly is then connected to a probe to carry out the testing procedures.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: March 17, 2009
    Assignee: Teradyne, Inc.
    Inventors: Frank B. Parrish, Arash Behziz
  • Patent number: 4829236
    Abstract: Calibrating a plurality of digital-to-analog converters using a calibration memory for storing calibration characteristics for respective digital-to-analog converters so as to provide uniform analog responses to digital data, and a calibrator to receive original digital data and to adjust it utilizing the stored calibration characteristics to produce adjusted digital data that, when inputted into a digital-to-analog converter, produce an analog signal that corresponds to the original digital data.
    Type: Grant
    Filed: October 30, 1987
    Date of Patent: May 9, 1989
    Assignee: Teradyne, Inc.
    Inventors: Ara Brenardi, Frank B. Parrish