Abstract: A device for regulating the air volume flow for a laboratory exhaust, has a rectangular housing (6) which can be arranged on the laboratory exhaust. The device is equipped with inflow devices that can be connected to the interior of the laboratory exhaust and with outflow devices (8, 12, 13) that can be connected to an exhaust air system. The interior of housing (6) is divided by a partition (17) into two parts, namely a calming part on the exhaust side and a measurement and regulating part on the outflow side, and these two parts are connected by an air deflection area (18). A rectangular measurement orifice (20, 25) has pressure measurement devices (22, 23, 24, 28, 29) and a rectangular regulating flap (21) arranged one after the other at a distance in the direction of flow between a housing wall and the partition (17).

Abstract: A combined ATA and SATA controller is provided that comprises a control unit for controlling data transfer to and/or from an ATA compliant parallel storage device and a control unit for controlling data transfer to and/or from an SATA compliant serial storage device. The controller can concurrently perform the data transfer to and/or from the parallel and serial devices. By reusing a significant amount of controller hardware, the combined controller can be realized in a cost effective manner.

Abstract: An interrupt handling technique is provided that may allow for sharing level sensitive interrupts in systems where interrupts are message based, i.e., edge triggered. An interrupt input unit is provided for receiving level sensitive interrupt requests and generating request occurrence signals therefrom. An edge detection unit generates start signals for edge triggered interrupt messages on the basis of the request occurrence signals. An interrupt termination detection unit receives termination signals each indicating that an interrupt routine relating to a previous edge triggered interrupt message has terminated. The interrupt input unit is controlled to output a request occurrence signal in response to a received termination signal if a previously received level sensitive interrupt request is still active. That is, a second edge triggered interrupt message may be generated.

Abstract: A storage device host controller such as an SATA (Serial ATA) host controller and a corresponding method are provided for performing host-to-device and device-to-host communications in a PIO (Programmed I/O) data transfer mode and a DMA (Direct Memory Access) data transfer mode. The host controller comprises a buffer unit for buffering data and a data stream selection unit for selecting a data stream for submission to the buffer unit. The data stream selection unit is connected to receive at any one time at least one of a host-to-device data stream in the PIO data transfer mode, a host-to-device data stream in the DMA data transfer mode, a device-to-host data stream in the PIO data transfer mode, and a device-to-host data stream in the DMA data transfer mode, and select from the received data streams the data stream to be submitted to the buffer unit.

Abstract: An on-chip event timer apparatus including a hardware timer and a debug interface. The hardware timer includes at least an up-counter for counting clocks of a clock signal, a match register for storing a programmable count value, and a comparator for monitoring whether the up-counter's count value matches the count value of the match register. The debug interface includes enable control unit for enabling the up-counter's operation based on a pre-defined relationship between a state of an enabled signal supplied to said up-counter and an internal state of the hardware timer. Additionally, the debug interface may comprise a clock divider connected to the enable control unit to reduce the clock's frequency in accordance with a pre-programmed divider value. Based on the received clock with the reduced clock frequency, the enable control unit adapts the up-counter's processing speed to the reduced clock frequency.

Abstract: Device for regulating the air volume flow for a laboratory exhaust, comprising

Abstract: A command storage technique that fulfils ordering rules is provided. This technique may be used in HyperTransport compliant southbridge devices. A command transmit engine comprises a command storage unit that is adapted to receive incoming commands of different command types and store the command in the order in which the commands were received. The command transmit engine further comprises an ordering rule controller that is connected to the command storage unit to select stored commands to be transmitted. The ordering rule controller is adapted to perform the selection according to predefined command ordering rules. The command ordering rules are command type dependent.

Abstract: The invention relates generally to radix-r FFTs (Fast Fourier Transforms), and more particularly to a method and an apparatus for assigning data samples to memory when computing a radix-r FFT. In one embodiment, the apparatus comprises a plurality of memory banks for storing the data samples, a memory bank counter indicating the memory banks, a data sample counter for counting an increment of the data samples, a region difference counter for counting a region difference change of a butterfly stage, a computer program having the current values of the data sample counter and the region difference counter as input values for determining whether the fractional part of the current data sample value divided by the current region difference value equals zero, and a multiplexer for multiplexing the current data sample to an assigned memory bank if the fractional part is not equal zero.

Abstract: An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.

Abstract: An improved response reordering technique for use in a southbridge device or I/O hub or similar devices are provided. Non-posted read requests are received from at least one requestor, and upstream commands are transmitted based on the non-posted read requests. Each of the upstream commands is uniquely identified by a command tag. When response data is received in reply to previously transmitted commands, responses are transmitted to the at least one requestor based on the response data. Transmitting the responses comprises reordering the received response data by accessing a buffer of the southbridge device. The buffer stores the received response data and has a plurality of buffer elements that are each uniquely assigned to one of the command tags.

Abstract: An improved interface technology is provided that may be applied to PCI (Peripheral Component Interconnect) devices connected to a southbridge. Requests are received from at least one requestor. The request require responses to be sent back to the respective requestor. The requests are placed by the respective requestor by asserting a request signal, and the request signal is deasserted by the respective requestor when a response is sent back. A retry request may be sent to the current requestor for requesting the current requestor to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later. Together with the retry request, a ready signal is sent indicating whether the request could be processed. This allows the requestor to modify its request when retrying it, if the request was not yet processed.

Abstract: An on-chip event timer apparatus including a hardware timer and a debug interface. The hardware timer includes at least an up-counter for counting clocks of a clock signal, a match register for storing a programmable count value, and a comparator for monitoring whether the up-counter's count value matches the count value of the match register. The debug interface includes enable control unit for enabling the up-counter's operation based on a pre-defined relationship between a state of an enabled signal supplied to said up-counter and an internal state of the hardware timer. Additionally, the debug interface may comprise a clock divider connected to the enable control unit to reduce the clock's frequency in accordance with a pre-programmed divider value. Based on the received clock with the reduced clock frequency, the enable control unit adapts the up-counter's processing speed to the reduced clock frequency.

Abstract: A method and apparatus for passing device configuration information to a shared controller. In one embodiment, a host controller may be configured to read configuration from one or more peripheral devices coupled to a serial bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device. Additional information needed to configure the device to communicate over the peripheral bus may also be obtained with a read of the device, or various lookup mechanisms, such as a lookup table or a tree-like data structure.

Abstract: An ATA (Advanced Technology Attachment) controller is provided that comprises at least one parallel port for connecting to at least one ATA compliant storage device, and at least one serial port for connecting to at least one SATA (Serial ATA) compliant storage device. Further, there is a port switching unit provided for switching to at least one of the parallel and serial ports to enable data transfer to and/or from a storage device connected to the port. This enables a software driven reconfiguration making it possible to switch between a mode where the controller behaves like a conventional ATA controller, and a mode where the controller behaves like a conventional SATA controller. A significant amount of hardware may be reused.

Abstract: A combined ATA and SATA controller is provided that comprises a control unit for controlling data transfer to and/or from an ATA compliant parallel storage device and a control unit for controlling data transfer to and/or from an SATA compliant serial storage device. The controller can concurrently perform the data transfer to and/or from the parallel and serial devices. By reusing a significant amount of controller hardware, the combined controller can be realized in a cost effective manner.

Abstract: An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit can store data relating to a request to be sent, and the second circuit unit cannot store data relating to a received request. Thus, an on-chip interface is provided that may increase the overall system performance and that may support split transaction.

Abstract: A PLL circuit is provided that comprises a frequency divider that generates a divided frequency signal and a phase frequency detector that receives the divided frequency signal and a reference frequency signal and that is arranged for outputting a first signal for increasing the frequency of an output signal and a second signal for decreasing the frequency of the output signal. Further, there is provided a signal modification unit that receives the first and second signals and that comprises a pulse selector selecting a signal pulse in one of the first and second signals, and a pulse generator for generating a signal pulse simultaneously with the selected signal pulse and adding the generated signal pulse to the other one of the first and second signals.