Abstract: A circuit arrangement for protecting an electronic device from damage upon a fault. The circuit arrangement includes at least one first terminal, at least one second terminal, a first interface and a second interface, a fault detection circuit region, a fault signal processing circuit region, and a disconnection circuit region. The at least one first terminal is coupled to the at least one second terminal in a fault-free state, the fault detection circuit region is coupled to the fault signal processing circuit region, the fault signal processing circuit region is coupled to the disconnection circuit region, the disconnection circuit region is configured to disconnect at least one of the at least one first terminal and the at least one second terminal, and the fault detection circuit region, the first and second interfaces, and the disconnection circuit region are configured to be compatible with another different fault signal processing circuit region.

Abstract: A switching regulator circuit and a method for providing a regulated output voltage for a load is provided that includes a comparator, whose comparator output signal is routed to a first oscillator control input, whereby a first comparator input voltage is present at a first input of the comparator and a second comparator input voltage is present at a second comparator input of the comparator, an oscillator with the first oscillator control input, at which the comparator output signal of the comparator is present, and whereby an oscillator output signal can be provided at an output of the oscillator, and by means of the signal the switching processes at a switching element can be controlled, by which a coil current can be influenced by a coil connected to the switching element, and a first compensator for influencing the second comparator input voltage as a function of the input voltage, whereby this first compensator is connected to the second comparator input of the comparator.

Abstract: A circuit arrangement for protecting an electronic device from damage upon a fault. The circuit arrangement includes at least one first terminal, at least one second terminal, a first interface and a second interface, a fault detection circuit region, a fault signal processing circuit region, and a disconnection circuit region. The at least one first terminal is coupled to the at least one second terminal in a fault-free state, the fault detection circuit region is coupled to the fault signal processing circuit region, the fault signal processing circuit region is coupled to the disconnection circuit region, the disconnection circuit region is configured to disconnect at least one of the at least one first terminal and the at least one second terminal, and the fault detection circuit region, the first and second interfaces, and the disconnection circuit region are configured to be compatible with another different fault signal processing circuit region.