Abstract: A radio communication system comprises a radio transmitter (2), and a radio receiver (12) configured to receive radio transmissions from the transmitter. The transmitter (2) uses a transmitter clock signal to transmit a succession of connection-event data packets (22a?, 22b?, 22c?) according to a predetermined schedule. The receiver (12) enters a sleep state between receiving successive connection-event data packets from the transmitter (2), in which it does not receive and process radio transmissions from the transmitter. It uses a receiver clock signal to determine when a predetermined number of receiver clock cycles has elapsed after receiving one of the connection-event data packets (22b?), and then enters a ready state. The predetermined number of receiver clock cycles is the number of receiver clock cycles (34a) that elapsed between the respective receipts of two of the connection-event data packets (22a?, 22b?) received by the receiver (12) minus a correction factor (38).

Abstract: A system for streaming data packets, comprises a source device (2) having a radio transceiver (10), and a receiving device (4) having a radio transceiver (14). The source device (2) is configured to receive or generate a stream of data packets at a stream rate and to transmit, by radio, a succession of data frames, each data frame comprising a successive set of one or more data packets (22a) from the stream that have not previously been transmitted. The receiving device (4) is configured to receive a data frame and to determine whether the one or more data packets (22a) in the data frame have been correctly or incorrectly received and to transmit by radio an acknowledgement message (22c) indicating that one or more of the data packets (22a) has been correctly received and/or is configured to transmit by radio an acknowledgement message indicating that one or more of the data packets has been incorrectly received.

Abstract: Disclosed are a method of and apparatus for controlling a first radio transceiver 18 and a second radio transceiver 20 which are connected to a common oscillator 16, wherein each transceiver 18, 20 is capable of communicating with one or more remote radio transceivers 12, 14. The method comprises: the first transceiver 18 sending a synchronisation signal to the second transceiver 20; and the second transceiver 20 using the synchronisation signal to ensure that neither transceiver 18, 29 transmits data while the other transceiver is in a receiving state.

Abstract: Synchronized radio transceivers Disclosed are a method of and apparatus for controlling a first radio transceiver (18) and a second radio transceiver (20) which are connected to a common oscillator (16), wherein each transceiver (18, 20) is capable of communicating with one or more remote radio transceivers (12, 14). The method comprises: •the first transceiver (18) sending a synchronization signal to the second transceiver (20); and •the second transceiver (20) using the synchronization signal to en sure that neither transceiver (18, 20) transmits data while the other transceiver is in a receiving state.

Abstract: An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means (2) clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means (2) detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.

Abstract: An integrated-circuit device (1) comprises a processor (7), memory (13) for storing executable code, and memory protection logic (9). The memory protection logic (9) is configured to: determine the state of a read protection flag for a protected region of the memory (13); detect a memory read request by the processor (7); determine whether the read request is for an address in the protected region of the memory (13); determine whether the processor (7) issued the read request while executing code stored in the protected region of the memory (13); and deny read requests for addresses in the protected region if the read protection flag for the protected region is set, unless at least one of one or more access conditions is met, wherein one of the access conditions is that the processor (7) issued the read requests while executing code stored in the protected region.

Abstract: A radio communication system comprises a radio transmitter (2), and a radio receiver (12) configured to receive radio transmissions from the transmitter. The transmitter (2) uses a transmitter clock signal to transmit a succession of connection-event data packets (22a?, 22b?, 22c?) according to a predetermined schedule. The receiver (12) enters a sleep state between receiving successive connection-event data packets from the transmitter (2), in which it does not receive and process radio transmissions from the transmitter. It uses a receiver clock signal to determine when a predetermined number of receiver clock cycles has elapsed after receiving one of the connection-event data packets (22b?), and then enters a ready state. The predetermined number of receiver clock cycles is the number of receiver clock cycles (34a) that elapsed between the respective receipts of two of the connection-event data packets (22a?, 22b?) received by the receiver (12) minus a correction factor (38).

Abstract: An integrated-circuit device (1) comprises a processor (7), memory (13) for storing executable code, and memory protection logic (9). The memory protection logic (9) is configured to: determine the state of a read protection flag for a protected region of the memory (13); detect a memory read request by the processor (7); determine whether the read request is for an address in the protected region of the memory (13); determine whether the processor (7) issued the read request while executing code stored in the protected region of the memory (13); and deny read requests for addresses in the protected region if the read protection flag for the protected region is set, unless at least one of one or more access conditions is met, wherein one of the access conditions is that the processor (7) issued the read requests while executing code stored in the protected region.

Abstract: A radio communication system comprises a radio transmitter (2), and a radio receiver (12) configured to receive radio transmissions from the transmitter. The transmitter (2) uses a transmitter clock signal to transmit a succession of connection-event data packets (22a?, 22b?, 22c?) according to a predetermined schedule. The receiver (12) enters a sleep state between receiving successive connection-event data packets from the transmitter (2), in which it does not receive and process radio transmissions from the transmitter. It uses a receiver clock signal to determine when a predetermined number of receiver clock cycles has elapsed after receiving one of the connection-event data packets (22b?), and then enters a ready state. The predetermined number of receiver clock cycles is the number of receiver clock cycles (34a) that elapsed between the respective receipts of two of the connection-event data packets (22a?, 22b?) received by the receiver (12) minus a correction factor (38).

Abstract: A stereoscopic viewing apparatus (16) is synchronized with a display (2). A signal(8) generated by or synchronised with the display (16) is transmitted. The signal (8) comprises a sequence of data packets (204), wherein each data packet (202a-e) in the sequence comprises an identifying portion of data. The stereoscopic viewing apparatus (16) receives a data packet (202b) from the sequence of data packets (204). A position of the data packet (202b) in the sequence of data packets (204)is identified using said identifying portion. Timing information related to the data packet (202b) is determined using said position. The timing information is used for synchronization of the stereoscopic viewing apparatus(16) with the display (2) and for determining when to activate a receiver(22) in the stereoscopic viewing apparatus (16) for receiving a subsequent packet.

Abstract: A system for streaming data packets, comprises a source device (2) having a radio transceiver (10), and a receiving device (4) having a radio transceiver (14). The source device (2) is configured to receive or generate a stream of data packets at a stream rate and to transmit, by radio, a succession of data frames, each data frame comprising a successive set of one or more data packets (22a) from the stream that have not previously been transmitted. The receiving device (4) is configured to receive a data frame and to determine whether the one or more data packets (22a) in the data frame have been correctly or incorrectly received and to transmit by radio an acknowledgement message (22c) indicating that one or more of the data packets (22a) has been correctly received and/or is configured to transmit by radio an acknowledgement message indicating that one or more of the data packets has been incorrectly received.

Abstract: An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means (2) clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means (2) detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.

Abstract: A radio communication system comprises a radio transmitter (2), and a radio receiver (12) configured to receive radio transmissions from the transmitter. The transmitter (2) uses a transmitter clock signal to transmit a succession of connection-event data packets (22a?, 22b?, 22c?) according to a predetermined schedule. The receiver (12) enters a sleep state between receiving successive connection-event data packets from the transmitter (2), in which it does not receive and process radio transmissions from the transmitter. It uses a receiver clock signal to determine when a predetermined number of receiver clock cycles has elapsed after receiving one of the connection-event data packets (22b?), and then enters a ready state. The predetermined number of receiver clock cycles is the number of receiver clock cycles (34a) that elapsed between the respective receipts of two of the connection-event data packets (22a?, 22b?) received by the receiver (12) minus a correction factor (38).

Abstract: Synchronised radio transceivers Disclosed are a method of and apparatus for controlling a first radio transceiver (18) and a second radio transceiver (20) which are connected to a common oscillator (16), wherein each transceiver (18, 20) is capable of communicating with one or more remote radio transceivers (12, 14). The method comprises: —the first transceiver (18) sending a synchronisation signal to the second transceiver (20); and—the second transceiver (20) using the synchronisation signal to en sure that neither transceiver (18, 20) transmits data while the other transceiver is in a receiving state.

Abstract: An integrated-circuit device (1) comprises a processor (7), memory (13) for storing executable code, and memory protection logic (9). The memory protection logic (9) is configured to: determine the state of a read protection flag for a protected region of the memory (13); detect a memory read request by the processor (7); determine whether the read request is for an address in the protected region of the memory (13); determine whether the processor (7) issued the read request while executing code stored in the protected region of the memory (13); and deny read requests for addresses in the protected region if the read protection flag for the protected region is set, unless at least one of one or more access conditions is met, wherein one of the access conditions is that the processor (7) issued the read requests while executing code stored in the protected region.