Patents by Inventor Frank (Bin) Yang
Frank (Bin) Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8293609Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.Type: GrantFiled: January 20, 2012Date of Patent: October 23, 2012Assignee: GLOBALFOUNDRIES, Inc.Inventors: Rohit Pal, Frank Bin Yang, Michael J. Hargrove
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Patent number: 8217463Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.Type: GrantFiled: February 4, 2011Date of Patent: July 10, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Rohit Pal, Michael Hargrove, Frank Bin Yang
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Patent number: 8193592Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.Type: GrantFiled: October 14, 2010Date of Patent: June 5, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Frank Bin Yang, Andrew M. Waite, Scott Luning
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Publication number: 20120129311Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.Type: ApplicationFiled: January 20, 2012Publication date: May 24, 2012Applicant: GLOBALFOUNDRIES Inc.Inventors: Rohit PAL, Frank Bin YANG, Michael J. HARGROVE
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Patent number: 8148750Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.Type: GrantFiled: March 21, 2011Date of Patent: April 3, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Rohit Pal, Frank Bin Yang, Michael J. Hargrove
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Patent number: 8120120Abstract: Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 ? to 28 about 800 ?, and the first and second layers at a thickness of about 30 ? to about 70 ?.Type: GrantFiled: September 17, 2009Date of Patent: February 21, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank (Bin) Yang, Johan W. Weijtmans, Scott Luning
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Patent number: 8076209Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.Type: GrantFiled: April 30, 2010Date of Patent: December 13, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Frank Bin Yang, Rohit Pal, Michael J. Hargrove
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Patent number: 8026539Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.Type: GrantFiled: February 18, 2009Date of Patent: September 27, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Michael Hargrove, Frank Bin Yang, Rohit Pal
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Publication number: 20110204446Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Frank Bin YANG, Rohit PAL, Scott LUNING
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Patent number: 7994014Abstract: The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.Type: GrantFiled: October 10, 2008Date of Patent: August 9, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Frank Bin Yang, Rohit Pal, Michael J. Hargrove
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Publication number: 20110169073Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.Type: ApplicationFiled: March 21, 2011Publication date: July 14, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Rohit PAL, Frank Bin YANG, Michael J. HARGROVE
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Patent number: 7960229Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.Type: GrantFiled: April 10, 2008Date of Patent: June 14, 2011Assignee: GlobalFoundries Inc.Inventors: Frank Bin Yang, Rohit Pal, Scott Luning
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Publication number: 20110121397Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.Type: ApplicationFiled: February 4, 2011Publication date: May 26, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Rohit PAL, Michael HARGROVE, Frank Bin YANG
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Patent number: 7939852Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.Type: GrantFiled: July 21, 2008Date of Patent: May 10, 2011Assignee: GlobalFoundries Inc.Inventors: Rohit Pal, Frank Bin Yang, Michael J. Hargrove
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Publication number: 20110095341Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.Type: ApplicationFiled: October 22, 2009Publication date: April 28, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Rohit Pal, Michael Hargrove, Frank Bin Yang
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Patent number: 7932143Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.Type: GrantFiled: October 22, 2009Date of Patent: April 26, 2011Assignee: GlobalFoundries Inc.Inventors: Rohit Pal, Michael Hargrove, Frank Bin Yang
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Publication number: 20110062498Abstract: Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 ? to 28 about 800 ?, and the first and second layers at a thickness of about 30 ? to about 70 ?.Type: ApplicationFiled: September 17, 2009Publication date: March 17, 2011Inventors: Frank (Bin) Yang, Johan W. Weijtmans, Scott Luning
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Publication number: 20110024841Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.Type: ApplicationFiled: October 14, 2010Publication date: February 3, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Frank Bin YANG, Andrew M. WAITE, Scott LUNING
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Patent number: 7829401Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.Type: GrantFiled: May 15, 2008Date of Patent: November 9, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Frank Bin Yang, Andrew M. Waite, Scott Luning
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Publication number: 20100210084Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.Type: ApplicationFiled: April 30, 2010Publication date: August 19, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Frank Bin YANG, Rohit PAL, Michael J. HARGROVE