Abstract: A system and method of deterministically transferring data across a first clock domain to a second clock domain includes receiving a resynchronize command, initiating a corresponding one of a plurality of read delays in each one of a second plurality of devices in the second clock domain, counting down the plurality of read delays to zero, receiving a training pattern after the plurality of read delays count down to zero in each one of the second plurality of devices, recovering a clock data in each of the second plurality of devices, receiving a synch byte by each of the second plurality of devices, selecting one of a plurality of serial lanes as a reference lane, wherein the plurality of serial lanes couple the first clock domain to the second clock domain, initiating a write pointer, writing n bytes of serial data to a buffer and converting the n bytes of data from serial data to parallel data in a serial to parallel converter such that the serial n byte data in the buffer are aligned in time.

Abstract: A system and method of deterministically transferring data from a first clock domain to a second clock domain includes writing data to a buffer, communicating a read status from the first clock domain to the second clock domain and reading data from the buffer into the second clock domain at a clock rate of the second domain. The buffer is accessible by both one or more devices in each of the first clock domain and the second clock domain and the read status is communicated from the first clock domain to the second clock domain when the second clock domain enables the read status to be communicated from the first clock domain to the second clock domain.

Abstract: A circuit for deterministic unparking of a strand of a microprocessor having multiple clock domains is described. The circuit includes a first flip-flop and a second flip-flop. Each flip-flop has a data input connected to receive a respective unpark signal, a clock signal at respective clock frequencies, and a respective enable signal. Each enable signal is generated by a respective logic block, each including a counter and each operating at a respective one of the clock frequencies. The second flip-flop has a data input connected to an output of the first flip-flop, and outputs an unpark signal that is used to unpark a strand of the microprocessor in a deterministic manner.

Abstract: A system and method of deterministically transferring data across a first clock domain to a second clock domain includes receiving a resynchronize command, initiating a corresponding one of a plurality of read delays in each one of a second plurality of devices in the second clock domain, counting down the plurality of read delays to zero, receiving a training pattern after the plurality of read delays count down to zero in each one of the second plurality of devices, recovering a clock data in each of the second plurality of devices, receiving a synch byte by each of the second plurality of devices, selecting one of a plurality of serial lanes as a reference lane, wherein the plurality of serial lanes couple the first clock domain to the second clock domain, initiating a write pointer, writing n bytes of serial data to a buffer and converting the n bytes of data from serial data to parallel data in a serial to parallel converter such that the serial n byte data in the buffer are aligned in time.

Abstract: The present invention provides an instruction fetch unit aligner. In one embodiment, an apparatus for an instruction fetch unit aligner includes selection logic for selecting a non-power of two size instruction from power of two size instruction data, and control logic for controlling the selection logic.

Abstract: The present invention provides an instruction fetch unit aligner. In one embodiment, an apparatus for an instruction fetch unit aligner includes selection logic for selecting a non-power of two size instruction from power of two size instruction data, and control logic for controlling the selection logic.

Abstract: The present invention provides an instruction fetch unit aligner. In one embodiment, an apparatus for an instruction fetch unit aligner includes selection logic for selecting a non-power of two size instruction from power of two size instruction data, and control logic for controlling the selection logic.