Abstract: A cascode logic design methodology for producing cascode current switch products utilizing Field Effect transistors wherein the field Effect transistors as voltage mode devices serve as current mode devices.

Abstract: The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array employing CTS (Complementary Transistor Switch) type memory cells.

Abstract: A bipolar transistor integrated circuit PLA is disclosed. The array includes a first and second mutually isolated epitaxial regions in a semiconductor substrate. A plurality of common collector bipolar transistors are formed in the first epitaxial region with selected ones of the plurality having their emitters connected in common to a first current source. A second plurality of common collector bipolar transistors in the second epitaxial region have the emitters of selected ones of the second plurality connected in common to the first epitaxial region. The bases of the corresponding pairs of transistors from the first and second epitaxial region are connected to an input signal source. The second epitaxial region is connected to an output node. In this manner, a cascode connected PLA is formed which eliminates the need for surplus current sources required in the prior art. The dot OR formed by the circuit effectively merges the prior art OR array with the search array.