Abstract: A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subjected to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and a horizontal fill portion of the spacer layer remains in one more recesses present in the STI regions so as to substantially planarize the STI region prior to subsequent material deposition thereon.

Abstract: A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subjected to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and a horizontal fill portion of the spacer layer remains in one more recesses present in the STI regions so as to substantially planarize the STI region prior to subsequent material deposition thereon.

Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.

Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.

Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.