Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: A data processing system includes a mechanism to periodically idle the normal system operation to allow recalibration of its interface circuitry by transmission of data with transitions and logic levels indicative of actual operation. Provision is made to protect actual data of the system from corruption during recalibration.

Abstract: A method and apparatus for interface signaling using single-ended and differential data signals improves performance of an interface. A differential pair of data signals and at least one single-ended data signal are transmitted over the interface. The differential pair of data signals is received by a differential receiver and the single-ended data signals are received by a receiver that uses the differential pair of data signals to improve the detection of the single-ended data signal. A novel receiver having a differential input and a single-ended input combines the differential pair of data signals with a single-ended data signal to detect the single-ended data signal providing improved common-mode rejection and reducing the error rate of the single-ended signal. Multiple single-ended signals may be associated with one differential signal, providing a scalable architecture grouping a number of single-ended signals with each differential pair of signals.

Abstract: A method and system for dynamic synchronization of a data processing system processor chips. One of a plurality of chips is designated as a primary chip and all other chips as secondary chips. The clock phase of the chips are synchronized utilizing the primary chip's clock phase as a reference clock phase for the secondary chips.

Abstract: A method and system for increasing speeds of transferring data in a data transfer system which includes a data source and data sink. Both the data source and data sink include clocks which are synchronized to a common clock frequency. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided within the data sink which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink.

Abstract: A programmable delay element having a fine delay circuit with fractional units of delay. The fine delay circuit has a fine delay circuit with a plurality of selectable delay paths, each delay path having an associated delay interval. The fine delay element is electrically-coupled to a data terminal for receiving and delaying an input signal. A control circuit is electrically-coupled to the fine delay circuit to select the delay path for the input signal. In a further aspect of the invention, the fine delay circuit is electrically-coupled to a coarse delay circuit having a plurality of selectable delay blocks in a repetitive block configuration. The coarse delay circuit is electrically-coupled to a second data terminal for receiving and inserting a second signal through said fine delay circuit. The control circuit is electrically-coupled to the selective delay path of the fine delay circuit and the coarse delay circuit such that either a fine delay, a coarse delay, or a coarse and a fine delay can be selected.

Abstract: A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0's on their drive interfaces, and setting all receive interfaces on the chips to receive 0's and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0's, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking 1 test is then repeated for any additional interfaces that require testing.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: An attached storage media link has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a high speed, cost effective interface to a direct access storage device.

Abstract: A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

Abstract: A first circuit and a second circuit are connected by a pumped signal line that conducts a signal having a plurality of states. A dynamic termination circuit is connected to the pumped signal line. The dynamic termination circuit includes a switch responsive to the signal conducted by the pumped signal line such that the dynamic termination circuit is enabled only in response to certain of the plurality of states of the signal. In one embodiment, the switch is a first transistor that is coupled in series with a first impedance between a first reference voltage and an intermediate node. In this embodiment, the dynamic termination circuit further includes a second transistor coupled in series with a second impedance between a second reference voltage and the intermediate node and only first and second inverters that are each coupled between the intermediate node and the control input of a respective one of the first transistor and the second transistor.

Abstract: Frequency differences between differing clock sources are compensated for by an adaptive filtering mechanism. An amount of frequency drift between two clock sources is determined. Then, based on that amount of frequency drift, a filtering value is selected to be used in tracking the frequency drift. If the frequency drift is determined to be large, then a minimum filtering value is selected. However, if it is determined to be small, then a maximum filtering value is selected. The selected filtering value is used to adjust the address(es) of one or more data bits being transmitted and received using the two clock sources, such that the frequency drift is properly tracked.

Abstract: Frequency differences between differing clock sources are compensated for by an adaptive filtering mechanism. An amount of frequency drift between two clock sources is determined. Then, based on that amount of frequency drift, a filtering value is selected to be used in tracking the frequency drift. If the frequency drift is determined to be large, then a minimum filtering value is selected. However, if it is determined to be small, then a maximum filtering value is selected. The selected filtering value is used to adjust the address(es) of one or more data bits being transmitted and received using the two clock sources, such that the frequency drift is properly tracked.

Abstract: According to the preferred embodiment, a phase-locked loop system is provided that overcomes the limitations of the prior art by providing the ability to switch output frequencies without a disruption in the phase lock of the output signal. The system uses a first phase-locked loop coupled with a second phase lock-loop such that their output signals are phase aligned and a switching mechanism for switching between the first phase lock output signal and the second phase lock loop output signal. The system is thus able to switch the frequency of its output without a disruption in the phase-lock of the signal.

Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

Abstract: According to the preferred embodiment of the present invention, a phase-locked loop is provided that overcomes the limitations of the prior art by facilitating fast locking on transition to a different output frequency. The phase-locked loop comprises an oscillator that provides a phase-locked loop output signal at various selected frequencies; a feedback divider; a phase comparator; a memory storage mechanism for storing phase-locked loop control information corresponding to selected output frequencies; and a digital circuit mechanism that receives the control information from the memory storage mechanism on transition to a different output frequency. The control information includes a digital counter value corresponding to the last recorded phase difference of the output signal at the different output frequency. On transition, this information is loaded directly to the digital circuit mechanism, reducing the need and time required for the phase comparator operation to drive the PLL to lock.

Abstract: A serial data stream is recovered using a local clock, which is asynchronous to the clock used to transmit the serial data. The incoming serial data stream is phase shifted or delayed by a digital phase-locked loop so that it may be reliably sampled by the local clock. The DPLL samples the serial data stream and captures data on both the rising and falling edges of the local clock employing three edge detectors. This partitions the data stream into two bit samples, which the DPLL presents to a deserializer. The deserializer converts the serial data to parallel data and assembles the received data back into data bytes. The deserializer also generates a received byte clock used for presenting the parallel data to, for example, the ESCON channel logic.

Abstract: A variable frequency oscillator circuit includes a ring oscillator circuit, a plurality of adjustment means for adjusting an output frequency of the ring oscillator circuit, at least one of the adjustment means having monotonic behavior, adapted to switch between first adjustment levels at a first rate and at least one of the adjustment means having non-monotonic behavior, adapted to switch between second adjustment levels at a second rate which is less than the first rate, such that the means having monotonic behavior adjusts for monotonicity errors which occur during switching.

Abstract: According to the preferred embodiment, an improved feedforward path is provided that improves the frequency response and reduces the output jitter of a phase-locked loop. Specifically, the frequency response is improved by providing a zero in the frequency response of the phase-locked loop by means of a feedforward path. The feedforward path delivers a feedforward charge to the oscillator of the phase-locked loop. According to the preferred embodiment, the feedforward path reorders the feedforward charge, such that the feedforward charge is stored and distributed equally across all the phase-locked loop output signal sub-cycles.