Patents by Inventor Frank De Stasi

Frank De Stasi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7863869
    Abstract: A circuit for selectively regulating a current at one value from multiple defined values. The circuit includes a sense selector to select a current sense signal from multiple current sense signals and a current path selector to select a current pathway from multiple current pathways. Each current pathway is associated with a resistance value. The resistance value of the selected current pathway, in part, defines the value at which the output current is regulated to.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: January 4, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Frank De Stasi
  • Patent number: 7671574
    Abstract: A buck DC to DC converter is arranged to more accurately regulate an output voltage by substantially eliminating a ground voltage error caused at least in part by parasitic resistance during low side conversion/regulation. During high side conduction of the high side switch, the converter employs the output voltage for error correction. And during low side conduction of the low side switch, the converter employs a sampled and held version of the output voltage for error correction which enables the converter to eliminate the ground voltage error caused by parasitic resistance.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: March 2, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Alexander Burinskiy, Frank De Stasi
  • Patent number: 6850101
    Abstract: Single line synchronization enables two or more oscillators to be synchronized with each other by using only a single control line. The synchronization can be accomplished without any external components. A single external component can be used to lower the frequency of an oscillator as in a master/slave-synchronized system. The use of the single control line (which can be embodied using a single integrated circuit pin) reduces the die area in which synchronization circuitry is situated. The single pin interface and reduced die area are advantageous for many applications that require small packages with a limited number of pins.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: February 1, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Frank De Stasi