Patents by Inventor Frank Djennas

Frank Djennas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5734201
    Abstract: A low profile semiconductor device (24) is manufactured by mounting a semiconductor die (26) onto a substrate (28) using an interposer (30). The interposer couples an active surface (32) of the die (26) to conductive traces (33) on the top surface of the substrate. The interposer is directionally conductive so that electrical conductivity is limited to the z-direction through thickness of the interposer. The interposer both affixes the die to the substrate and provides the first level of interconnects for the device. The inactive surface (36) of the die can be exposed for efficient thermal dissipation. An optional heat spreader (50) may be added for increased thermal management. The device may be overmolded, glob-topped, capped, or unencapsulated. Separate die-attach and wire bonding processes are eliminated. A second level of interconnects are provided by either solder balls (38), solder columns (44), or pins (64).
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: March 31, 1998
    Assignee: Motorola, Inc.
    Inventors: Frank Djennas, Wilhelm Sterlin, Bennett A. Joiner, Jr.
  • Patent number: 5474958
    Abstract: A wire bondable plastic encapsulated semiconductor device (58) having no die supporting surface can be manufactured. In one embodiment, a semiconductor die (22) and a plurality of conductors (12) extending toward the periphery of the die are provided. The die is rigidly held in place on a workholder (60) with a vacuum (62) for the wire bonding process. Wire bonds (26) electrically connect the die to the conductors. The wire bonded die is then placed inside a mold cavity (64), and a resin encapsulated is transferred into the cavity under elevated temperature and pressure to form package body (70) around the die, the wire bonds and a portion of the conductors. Before the package body is formed, the die is supported solely by the the rigidity of the wire bonds since there is no die supporting surface connected to the conductors.
    Type: Grant
    Filed: May 4, 1993
    Date of Patent: December 12, 1995
    Assignee: Motorola, Inc.
    Inventors: Frank Djennas, Victor K. Nomi, John R. Pastore, Twila J. Reeves, Les Postlethwait
  • Patent number: 5424576
    Abstract: A semiconductor device (10) includes a lead frame (12) having tie bars (16). In one form of the invention, the tie bars are used to support a semiconductor die (20) to alleviate package cracking problems caused by stress and to provide a universal lead frame which is suitable for use with many different die sizes. In another embodiment, a semiconductor device (45) includes a lead frame (40) having a mini-flag (42) to accomplish these same objectives.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: June 13, 1995
    Assignee: Motorola, Inc.
    Inventors: Frank Djennas, Isaac T. Poku, Robert Yarosh
  • Patent number: 5327008
    Abstract: A semiconductor device (10) includes a lead frame (12) having tie bars (16). In one form of the invention, the tie bars are used to support a semiconductor die (20) to alleviate package cracking problems caused by stress and to provide a universal lead frame which is suitable for use with many different die sizes. In another embodiment, a semiconductor device (45) includes a lead frame (40) having a mini-flag (42) to accomplish these same objectives.
    Type: Grant
    Filed: March 22, 1993
    Date of Patent: July 5, 1994
    Assignee: Motorola Inc.
    Inventors: Frank Djennas, Isaac T. Poku, Robert Yarosh
  • Patent number: 5233222
    Abstract: A semiconductor device (30) utilizes a lead frame (32) having a window-frame flag (36). An opening (44) within the flag creates an interior edge (46) which is tapered, preferably to an angle .phi. that is between 55.degree. and 65.degree.. The tapered interior edge reduces boundary-layer separation of a resin molding compound during formation of a resin package body (42). Thus, voids in the resin packaging material near the interior edge of the flag are less likely to be formed.
    Type: Grant
    Filed: July 27, 1992
    Date of Patent: August 3, 1993
    Assignee: Motorola, Inc.
    Inventors: Frank Djennas, Alan H. Woosley
  • Patent number: 4883774
    Abstract: A process for flashing a thin layer of silver on metal leadframes using no mask steps and a minimal amount of silver. An unmasked metal leadframe is placed into a cleaning bath that includes silver in solution and has no outside electrical driving force to assist plating. The leadframe is removed from the cleaning bath once a uniform silver layer having a thickness of 100 to 1000 angstroms is plated thereon. The silver layer need not be exact and, therefore, it is not critical that the period of time the leadframe remains in the cleaning bath be exact.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: November 28, 1989
    Assignee: Motorola, Inc.
    Inventors: Frank Djennas, Curtis W. Mitchell