Abstract: An apparatus comprises a mass storage unit and a plurality of circuit modules including a machine learning module, a programmable state machine module, and input/output interfaces. Switching circuitry is configured to selectively couple the circuit modules. Configuration circuitry is configured to access configuration data from the mass storage unit and to operate the switching circuitry to connect the circuit modules according to the configuration data.

Abstract: A connection between a user device and a network server is established. Via the connection, a deep learning network is formed for a processing task. A first portion of the deep learning network operates on the user device and a second portion of the deep learning network operates on the network server. Based on cooperation between the user device and the network server, a boundary between the first portion and the second portion of the deep learning network is dynamically modified based on a change in a performance indicator that could affect the processing task.

Abstract: A transmitting device generates a nominally unguaranteed error-detection code for each sub-data packet of a data packet, and a nominally guaranteed error-detection code for the data packet. The transmitting device transmits to a receiving device the data packet including the sub-data packets thereof, the nominally guaranteed error detection codes for the sub-data packets, and the nominally guaranteed error-detection code for the data packet. For each sub-data packet, the receiving device uses the nominally unguaranteed error-detection code for each sub-data packet to determine whether the sub-data packet is erroneous. In response to determining that no sub-data packet is erroneous, the receiving device uses the nominally guaranteed error-detection code for the data packet to determine whether the data packet is erroneous.

Abstract: A transmitting device can compress a packet prior to transmitting the packet to a receiving device, which then decompresses the packet. The packet can be combined into a single combined packet with other packets within a transmission queue of the same type and that refer to consecutive memory block addresses. A header of the packet can be replaced with a reduced-size header including a sequence number and a flag indicating the header has been replaced with the reduced-size header, if the packet has a consecutive memory block address to that of the most recently transmitted packet. A payload of the packet may also be compressed.

Abstract: A transmitting device generates a nominally unguaranteed error-detection code for each sub-data packet of a data packet, and a nominally guaranteed error-detection code for the data packet. The transmitting device transmits to a receiving device the data packet including the sub-data packets thereof, the nominally guaranteed error detection codes for the sub-data packets, and the nominally guaranteed error-detection code for the data packet. For each sub-data packet, the receiving device uses the nominally unguaranteed error-detection code for each sub-data packet to determine whether the sub-data packet is erroneous. In response to determining that no sub-data packet is erroneous, the receiving device uses the nominally guaranteed error-detection code for the data packet to determine whether the data packet is erroneous.

Abstract: Systems and methods for encrypted processing are provided. For example, an apparatus for encrypted processing includes: an input interface adapted to receive input from a device; an encrypted processor connected to the input interface; a program store control connected to the encrypted processor, the program store control controlling use of and access to at least two program stores, where at least one program store acts as a primary program store and at least one program store acts as a back-up program store; and an output interface connected to the encrypted processor for outputting at least one of commands or data; where the encrypted processor is programmed to: receive and validate a request; determine whether a valid request is a program update request for a first program; and initiate a lock mechanism into a locked state.

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

Abstract: An apparatus comprises a mass storage unit and a plurality of circuit modules including a machine learning module, a programmable state machine module, and input/output interfaces. Switching circuitry is configured to selectively couple the circuit modules. Configuration circuitry is configured to access configuration data from the mass storage unit and to operate the switching circuitry to connect the circuit modules according to the configuration data.

Abstract: A connection between a user device and a network server is established. Via the connection, a deep learning network is formed for a processing task. A first portion of the deep learning network operates on the user device and a second portion of the deep learning network operates on the network server.

Abstract: A computing component may consist of a die package that has at least a board, first computing layer, and second computing layer. Dielectric layers can separate each of the board, first computing layer, and second computing layer. The first computing layer may be disposed between the board and second computing layer. One or more interconnects can continuously extend from the second computing layer to the board with a non-circular cross-section shape.

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

Abstract: A computing component may consist of a die package that has at least a board, first computing layer, and second computing layer. Dielectric layers can separate each of the board, first computing layer, and second computing layer. The first computing layer may be disposed between the board and second computing layer. One or more interconnects can continuously extend from the second computing layer to the board with a non-circular cross-section shape.

Abstract: A system includes a plurality of nonvolatile memory cells and a map that assigns connections between nodes of a neural network to the memory cells. Memory devices containing nonvolatile memory cells and applicable circuitry for reading and writing may operate with the map. Information stored in the memory cells can represent weights of the connections. One or more neural processors can be present and configured to implement the neural network.

Abstract: Hardware-enforced zoning is provided in Fibre Channel switches to protect against breaching of assigned zones in a switch network which can occur with software-based zoning techniques. The invention provides logic for performing a hardware-based validation of the Source ID S_ID of frames both at the point where the frame enters the Fibre Channel fabric, and at the point where the frame leaves the fabric. The S_ID is verified against an inclusion list or table of allowable S_IDs, which can be unique for each fabric port. The invention provides a way to increase the range of sources an inclusion table can express, by implementing wild cards, on an entry-by entry basis. If the S_ID is valid, it will enter the fabric and route normally. If invalid, the frame will not be routed but will be disposed of by the fabric according to FC rules.

Abstract: Hardware-enforced zoning is provided in Fibre Channel switches to protect against breaching of assigned zones in a switch network which can occur with software-based zoning techniques. The invention provides logic for performing a hardware-based validation of the Source ID S_ID of frames both at the point where the frame enters the Fibre Channel fabric, and at the point where the frame leaves the fabric. The S_ID is verified against an inclusion list or table of allowable S_IDs, which can be unique for each fabric port. The invention provides a way to increase the range of sources an inclusion table can express, by implementing wild cards, on an entry-by entry basis. If the S_ID is valid, it will enter the fabric and route normally. If invalid, the frame will not be routed but will be disposed of by the fabric according to FC rules.

Abstract: Method and system for processing frames in a fibre channel network is provided. The method includes, determining if an incoming frame in a port of a fibre channel switch includes a FR_Header with a time to live time (“TTLT”) field value; determining if the TTLT field value is greater than a certain number; adjusting the TTLT field value at a pre-determined time interval if the TTLT field value is greater than the certain number; and inserting an adjusted TTLT field value in the incoming frame before it is sent out. The switch element includes, a port that receives an incoming frame and determines if a FR_Header with a time to live time (“TTLT”) field value is received with the FR_Header, and using a timer adjusts the TTLT field value and inserts the adjusted TTLT field value in the incoming frame, before it is sent out.

Abstract: A fibre channel switch element and method for processing frames in a fibre channel network is provided. The switch element includes an address mapping cache that receives an incoming fibre channel frame in a receive and/or transmit segment, wherein the address mapping cache compares a D_ID of an incoming frame in the receive segment and/or a S_ID in the transmit segment; and if a FR_Header is received then a D_ID or S_ID is compared from a fibre channel header that follows the FR_Header; and if a compare fabric identifier flag is set, then the fabric identifier is compared. The address mapping cache may also be used for routing frames from one virtual fabric to another by comparing a VF_ID field to a Virtual fabric identifier in a VFT_Header.

Abstract: A method and device for transmitting a signal in an implantable medical device that includes a control unit and a first electrode and a second electrode positioned along a lead body. A connector block is positioned along an upper portion of a housing portion of the control unit, and a connector is positioned at a proximal portion of the lead body and is insertable within the connector block. A third electrode having a conductive element is positioned along the control unit in close proximity adjacent to the connector. The control unit transmits a signal between the first electrode and the second electrode and determines an alternate transmission path of the signal between the third electrode and one or both of the first electrode and the second electrode in response to the signal not being effectively transmitted between the first electrode and the second electrode.

Abstract: A high-speed Fibre Channel switch element in a Fibre Channel network is provided. The Fibre Channel switch element includes, a rate select module that allows a port in the Fibre Channel switch element to operate at a rate equal to and/or higher than 10 gigabits per second (“G”). The port may operate at 20G, 40G or at a rate greater than 40G. Also, a cut status is provided for cut-through routing between ports operating at different speed. Plural transmit and receive lines are used for port operation at a rate equal to or higher than 10G.

Abstract: A method and system for performing a copy operation between storage devices coupled to a Fibre Channel switch element is provided. The Fibre Channel switch element receives a user command to copy data from a source storage device to a destination storage device and controls the copying operation. The Fibre Channel switch acts as a SCSI initiator and initiates a write operation for the destination storage device and initiates a read operation for the source storage device; and uses an alias cache for intercepting messages between the destination and source storage devices. A RX_ID mapping cache is used to substitute a RX_ID so that that a Fibre Channel write target appears to the source storage device as the destination storage device, and to the destination storage device a Fibre Channel read target appears to be the source storage device.