Abstract: A new bus permits processing elements (PE's) to communicate with other PE's entirely under the control of each PE without a separate bus controller. Each PE has means for broadcasting its priority code on a contention portion of the bus and for sampling the bus after a delay in which it has received the codes from other PE's. Each PE holds its priority code on the bus for a further delay during which other PE's can sample the priority code. The PE's resolve contention for access to the information portion of the bus in a multi stage contention sequence. System usage, made possible by peer-to-peer distribution of bus access control, includes dynamic driven priority schemes, a variety of operating modes and hence flexible multiplexing of message traffic.

Abstract: This specification describes a set of arrays for performing logic function in various subsets of the original set. The array structure is characterized by a plurality of arrays joined together with a bidirectional bussing system. This bussing system comprises addressing lines of the arrays joined together by switching circuitry used to regroup the set into subsets as necessary to perform the logic functions.