Patents by Inventor Frank Edelhaeuser
Frank Edelhaeuser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10025704Abstract: A memory system includes a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing a program/erase (PE) count value, the PE count value indicating a number of PE cycles performed on the page. A PE count circuit is configured to perform a PE count read operation on a target page. A host determines whether to perform a data write operation on the target page or another PE count read operation on a new target page based on a result of the PE count read operation. PE cycles of a page are controlled by the PE count read operation. The memory array and the PE count circuit are formed in different layers of the substrate.Type: GrantFiled: December 27, 2013Date of Patent: July 17, 2018Assignee: CROSSBAR, INC.Inventor: Frank Edelhaeuser
-
Patent number: 9710191Abstract: Data associated with a logical block address (LBA) may be received from a host system to be stored in the memory array. The LBA may be translated to a physical block address (PBA) by determining a first portion of the PBA and a second portion of the PBA. The data from the host system may be stored in the buffer space after determining the first portion of the PBA and before determining the second portion of the PBA. The data from the buffer space may be flushed to the memory array after determining the second portion of the PBA.Type: GrantFiled: April 13, 2016Date of Patent: July 18, 2017Assignee: MONTEREY RESEARCH, LLCInventors: Frank Edelhaeuser, Clifford A. Zitlaw, Jeremy Mah
-
Patent number: 9489997Abstract: A memory system including a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing metadata. A compare circuit is configured to receive metadata retrieved from a plurality of pages sequentially and compare the retrieved metadata to a search pattern. The physical location of the page can be determined by finding the search pattern. The memory array and the compare circuit are formed in different layers of the substrate.Type: GrantFiled: July 3, 2013Date of Patent: November 8, 2016Assignee: Crossbar, Inc.Inventor: Frank Edelhaeuser
-
Patent number: 9317445Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.Type: GrantFiled: February 11, 2013Date of Patent: April 19, 2016Assignee: Cypress Semiconductor CorporationInventors: Frank Edelhaeuser, Clifford A Zitlaw, Jeremy Mah
-
Publication number: 20150186258Abstract: A memory system includes a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing a program/erase (PE) count value, the PE count value indicating a number of PE cycles performed on the page. A PE count circuit is configured to perform a PE count read operation on a target page. A host determines whether to perform a data write operation on the target page or another PE count read operation on a new target page based on a result of the PE count read operation. PE cycles of a page are controlled by the PE count read operation. The memory array and the PE count circuit are formed in different layers of the substrate.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Applicant: Crossbar, Inc.Inventor: Frank EDELHAEUSER
-
Patent number: 9059705Abstract: A non-volatile field programmable gate array includes a logic component, a transistor device comprising a gate structure, a first impurity region, and a second impurity region, the first impurity region coupled to the reconfigurable logic component, and a resistive switching device comprising a bottom electrode coupled to the first impurity region, a top electrode spatially extending in a first direction, and a resistive switching element coupled to the top electrode and to the bottom electrode at an intersecting region between the bottom electrode and the top electrode, wherein the resistive switching device stores a resistance state from a plurality of resistance states that indicates a configuration code for the reconfigurable logic component.Type: GrantFiled: June 30, 2011Date of Patent: June 16, 2015Assignee: CROSSBAR, INC.Inventor: Frank Edelhaeuser
-
Publication number: 20150012694Abstract: A memory system including a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing metadata. A compare circuit is configured to receive metadata retrieved from a plurality of pages sequentially and compare the retrieved metadata to a search pattern. The physical location of the page can be determined by finding the search pattern. The memory array and the compare circuit are formed in different layers of the substrate.Type: ApplicationFiled: July 3, 2013Publication date: January 8, 2015Inventor: Frank EDELHAEUSER
-
Patent number: 8386736Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.Type: GrantFiled: December 18, 2008Date of Patent: February 26, 2013Assignee: Spansion LLCInventors: Frank Edelhaeuser, Clifford A Zitlaw, Jeremy Mah
-
Publication number: 20100161935Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Inventors: Frank EDELHAEUSER, Clifford A. ZITLAW, Jeremy MAH
-
Patent number: 7286384Abstract: A stacked module device and corresponding module and method are provided where at least some modules have input ports connected to receive first resource related signals and output ports connected to provide second resource related signals. The first and second signals are different, and each module comprises a resource signal transformation unit for generating the second signal from the first signals. The resource signal transformation units of each module are of the same construction. Resources may be addresses. Further, a software configurable address assignment is provided.Type: GrantFiled: June 22, 2005Date of Patent: October 23, 2007Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Michael Wendt, Frank Schneider, Frank Edelhaeuser, Helmut Prengel
-
Publication number: 20060202712Abstract: A stacked module device and corresponding module and method are provided where at least some modules have input ports connected to receive first resource related signals and output ports connected to provide second resource related signals. The first and second signals are different, and each module comprises a resource signal transformation unit for generating the second signal from the first signals. The resource signal transformation units of each module are of the same construction. Resources may be addresses. Further, a software configurable address assignment is provided.Type: ApplicationFiled: June 22, 2005Publication date: September 14, 2006Inventors: Michael Wendt, Frank Schneider, Frank Edelhaeuser, Helmut Prengel
-
Publication number: 20060206745Abstract: A stacked module device and corresponding module and method are provided where at least some of the modules have access to resources. At least one of the at least some modules have assigned at least one of the resources and comprises assignment means which is adapted to assign at least one other resource to at least one other module. Further, a stacked bus system may be provided where each module has input and output terminals and an assignment unit to assign at least one other resource to at least one other module. The assignment unit supplies an output signal relating to the other resource to an output terminal corresponding in position to the input terminal receiving the input signal relating to the one resource.Type: ApplicationFiled: June 22, 2005Publication date: September 14, 2006Inventors: Helmut Prengel, Frank Edelhaeuser, Frank Schneider, Michael Wendt