Abstract: A delay correction circuit is described for use with an elastic store in a PCM time division multiplexed system. The relative position of the read and write addresses supplied to the elastic store are monitored. In the event that either the read or write addresses are overtaking the other and are within a predetermined range of addresses, either the read or write address source will be initialized at a predetermined time such that the read and write addresses have new relative position.

Abstract: A transmitter-receiver synchronizer is described for use in terminating T1 lines from a subscriber line switch at a central time division multiplexed switching system. A shared rate converter provides bidirectional data rate conversion between the 1.544 Mb/s T1 line and the 2.048 Mb/s switching system. Two buffer memories are used, each writing in at one rate, and reading out at another rate.

Abstract: A carrier terminal unit for interfacing 1.544 MHz PCM lines to a digital switch, wherein voice samples are switched at 2.048 MHz, provides bit synchronization, in-frame monitoring, delay equalization and correction, framing detection, and rate and format conversion. A common memory is utilized for the delay equalization and correction, framing detection and rate and format conversion functions. The memory acts as an elastic store for delay equalization. Delay correction is provided by monitoring the relative positions of the memory read and write addresses and initializing the write addresses after an overtaking of the read or write addresses by the other is detected. Rate and format conversion are provided by storing incoming PCM samples in the memory and reading the samples out in accordance with a predetermined sequence. Framing detection is provided by storing in memory every nth bit of three alternate frames of incoming data.

Abstract: A fault-tolerant clock signal distribution system for a plurality of equipment units is disclosed. Fault tolerance is achieved by independent bussing of clock signals from each of a pair of duplicated clock sources to a plurality of clock receiver units, each receiver unit associated with one of the plurality of equipment units and including sequential logic apparatus operative to examine the two clock signal trains bussed to the clock receiver unit and to ignore that signal train that phase lags the other. In case the phase leading clock source or its transmission bus fails, the remaining clock signal takes over. Because the outputs of the duplicated clock sources are distributed over separate busses, either source may comprise the phase-leading clock at any particular clock receiver unit.

Abstract: The data comprises 8-bit words, plus a leading bit as a start bit at a logic one, and a trailing bit for parity, for a total of 10 bits per group. A synchronizing circuit in the receiver selects a proper phase of clock signals for shifting the data bits into a shift register. An enable flip-flop for the synchronizing circuit is set in response to the start bit at the receiver input, and is reset when the start bit appears in the last bit position of the shift register.In a preferred embodiment, a clock signal is divided into three phases by a delay line. The synchronizing circuit has three flip-flops for selecting the phase when the enable flip-flop becomes set. These flip-flops enable gates for supplying the selected phase to the shift register. Delays are provided from the transmission line to the shift register and enable flip-flop inputs, so that the sampling is centered over each data bit.