Abstract: A method of forming a metal-graphene composite includes coating metal components (10) with graphene (14) to form graphene-coated metal components, combining a plurality of the graphene-coated metal components to form a precursor workpiece (26), and working the precursor workpiece (26) into a bulk form (30) to form the metal-graphene composite. A metal-graphene composite includes graphene (14) in a metal matrix wherein the graphene (14) is single-atomic layer or multi-layer graphene (14) distributed throughout the metal matrix and primarily (but not exclusively) oriented with a plane horizontal to an axial direction of the metal-graphene composite.

Abstract: A method of forming a metal-graphene composite includes coating metal components (10) with graphene (14) to form graphene-coated metal components, combining a plurality of the graphene-coated metal components to form a precursor workpiece (26), and working the precursor workpiece (26) into a bulk form (30) to form the metal-graphene composite. A metal-graphene composite includes graphene (14) in a metal matrix wherein the graphene (14) is single-atomic layer or multi-layer graphene (14) distributed throughout the metal matrix and primarily (but not exclusively) oriented with a plane horizontal to an axial direction of the metal-graphene composite.

Abstract: A method of forming a metal-graphene composite includes coating metal components (10) with graphene (14) to form graphene-coated metal components, combining a plurality of the graphene-coated metal components to form a precursor workpiece (26), and working the precursor workpiece (26) into a bulk form (30) to form the metal-graphene composite. A metal-graphene composite includes graphene (14) in a metal matrix wherein the graphene (14) is single-atomic layer or multi-layer graphene (14) distributed throughout the metal matrix and primarily (but not exclusively) oriented with a plane horizontal to an axial direction of the metal-graphene composite.

Abstract: A hot extrusion die tool and a method of making the hot extrusion die tool are provided. The hot extrusion die tool includes a die tool component including a nickel-based super alloy; and a wear resistant coating deposited on the die tooling component. The method of making the hot extrusion die tool includes coating at least one portion of an extrusion die tool component comprising a nickel-based super alloy with a wear resistant coating at a high temperature; and hardening the extrusion die tool component and the at least one coated portion.

Abstract: This disclosure provides systems, methods and apparatus related to biometric authentication of a user of an electronic device. An electronic display has a display cover glass with a front surface that includes a viewing area, and a fingerprint reading area within the viewing area. At least one photosensing element is configured to detect received scattered light, the received scattered light resulting from interaction of light with an object in at least partial optical contact with the front surface within the fingerprint reading area and to output, to a processor, fingerprint image data.

Abstract: A hot extrusion die tool and a method of making the hot extrusion die tool are provided. The hot extrusion die tool includes a die tool component including a nickel-based super alloy; and a wear resistant coating deposited on the die tooling component. The method of making the hot extrusion die tool includes coating at least one portion of an extrusion die tool component comprising a nickel-based super alloy with a wear resistant coating at a high temperature; and hardening the extrusion die tool component and the at least one coated portion.

Abstract: This disclosure provides systems, methods and apparatus related to biometric authentication of a user of an electronic device. An electronic display has a display cover glass with a front surface that includes a viewing area, and a fingerprint reading area within the viewing area. At least one photosensing element is configured to detect received scattered light, the received scattered light resulting from interaction of light with an object in at least partial optical contact with the front surface within the fingerprint reading area and to output, to a processor, fingerprint image data.

Abstract: An active torque biasing differential includes a housing and an outer annulus disposed within the housing. An inner annulus is contained within the outer annulus. The inner annulus includes a plurality of slots. A plurality of vanes are disposed in the slots in the inner annulus. The vanes slidably contact the outer annulus. The vanes include a plurality of orifices formed therein. An electromagnetic coil is placed to apply a magnetic field to a chamber bounded by the outer annulus and inner annulus.

Abstract: A processor clock control device operable to control a plurality of clock signals output to a processor,- said processor comprising a plurality of domains each clocked by a respective one of said plurality of clock signals, said processor being operable in different modes including a functional mode and a test mode, said processor clock control device comprising: a clock signal input operable to receive a slower reference clock signal or a higher speed operational clock signal; at least two clock signal outputs each operable to output a clock signal to a respective domain of said processor; a mode control signal input operable to receive a mode control signal indicating a mode of operation of said processor; a launch control signal input operable to receive a launch control signal, said launch control signal indicating portions of said processor to be tested; and an initiation signal input operable to receive an initiation signal indicating initiation of a processor test; wherein said processor clock control

Abstract: An integrated circuit and method for testing memory on that integrated circuit are provided. The integrated circuit comprises processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided which is operable to execute test events in order to seek to detect any memory defects in the number of memory units. The memory test controller comprises a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the memory test controller is then operable, following the single programming operation, to execute the sequence of test events.

Abstract: A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.

Abstract: A packable seating apparatus having a single planar surface with a seat attached thereto, wherein the lower portion of the planar surface forms legs which raise the seat portion from the ground. The apparatus has storage compartments formed therein, support for a sleeping bag, and a color change device. The apparatus further utilizes any convenient surface, such as a tree or the like, as an additional support. In an alternate embodiment, the present invention includes a kickstand to allow free-standing support.

Abstract: In order to test the memory access signal connections between a data processing circuit, such as a processor core 2, and a memory 4, a subset of memory access signal connections 8 are provided with associated scan chain cells 10 so that they may be directly tested. The remainder memory access signal connections 12 which are common to all the expected configurations of the memory 4 are tested by being driven by the processor core 2 itself with data being passed through the memory and captured back within the processor core 2 for checking.

Abstract: Embodiments of the present invention relate generally to scan clock waveform generation. One embodiment utilizes global and local circular shift registers to provide a series of shift/capture pulses at a manageable frequency for the tester and launch pulses that are phase shifted in order to provide for at-speed testing. Therefore, scan test patterns may be shifted in or out of state elements at lower frequencies as compared to the normal operating frequency of the integrated circuit being tested, while still allowing for at-speed testing. An alternate embodiment utilizes a circular shift register in combination with static storage devices and waveform generators to provide the shift/capture pulses and launch pulses. Embodiments of the present invention also allow for clock inversion where the clock and clock bar signals are dependent during normal mode and independent during scan test mode.

Abstract: Embodiments of the present invention relate generally to scan clock waveform generation. One embodiment utilizes global and local circular shift registers to provide a series of shift/capture pulses at a manageable frequency for the tester and launch pulses that are phase shifted in order to provide for at-speed testing. Therefore, scan test patterns may be shifted in or out of state elements at lower frequencies as compared to the normal operating frequency of the integrated circuit being tested, while still allowing for at-speed testing. An alternate embodiment utilizes a circular shift register in combination with static storage devices and waveform generators to provide the shift/capture pulses and launch pulses. Embodiments of the present invention also allow for clock inversion where the clock and clock bar signals are dependent during normal mode and independent during scan test mode.