Patents by Inventor Frank G. KUECHENMEISTER
Frank G. KUECHENMEISTER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11907623Abstract: A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.Type: GrantFiled: January 26, 2021Date of Patent: February 20, 2024Assignee: GlobalFoundries Dresden Module One Limited Liability Company & Co. KGInventors: Saquib B. Halim, Marcel B. Wieland, Frank G. Kuechenmeister
-
Publication number: 20240030160Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.Type: ApplicationFiled: October 2, 2023Publication date: January 25, 2024Inventors: Nicholas A. Polomoff, Frank G. Kuechenmeister, Richard F. Taylor, III, Saquib B. Halim
-
Patent number: 11855005Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.Type: GrantFiled: June 21, 2021Date of Patent: December 26, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Nicholas A. Polomoff, Frank G. Kuechenmeister, Richard F. Taylor, III, Saquib B. Halim
-
Patent number: 11804440Abstract: Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer.Type: GrantFiled: January 28, 2021Date of Patent: October 31, 2023Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Saquib B. Halim, Frank G. Kuechenmeister, Kashi V Machani, Christian Goetze
-
Patent number: 11740418Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) structure with a passage for a waveguide through a barrier structure. The PIC structure includes a barrier structure on a substrate, having a first sidewall and a second sidewall opposite the first sidewall. A passage is within the barrier structure, and extends from a first end at the first sidewall of the barrier structure to a second end at the second sidewall of the barrier structure. A shape of the passage includes a reversal segment between the first end and the second end. A waveguide within the passage and extends from the first end to the second end of the barrier structure.Type: GrantFiled: March 23, 2021Date of Patent: August 29, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Nicholas A. Polomoff, John J. Ellis-Monaghan, Frank G. Kuechenmeister, Jae Kyu Cho, Michal Rakowski
-
Publication number: 20230238336Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Inventors: Ranjan RAJOO, Frank G. KUECHENMEISTER, Dirk BREUER
-
Patent number: 11652069Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.Type: GrantFiled: December 8, 2020Date of Patent: May 16, 2023Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ranjan Rajoo, Frank G. Kuechenmeister, Dirk Breuer
-
Patent number: 11557421Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. The IC structure may include a first metal layer on a substrate, and a second metal layer on the substrate that is horizontally separated from the first metal layer. A dielectric material may include a first portion on the first metal layer, and having a first upper surface, a second portion on the second metal layer, and having a second upper surface, and a third portion on the substrate between the first metal layer and the second metal layer. The third portion of the dielectric material includes a third upper surface above the first upper surface of the first portion and the second upper surface of the second portion of the dielectric material.Type: GrantFiled: March 5, 2020Date of Patent: January 17, 2023Assignee: GlobalFoundries Dresden Module One Limited Liability Company & Co. KGInventors: Frank G. Küchenmeister, Marcel B. Wieland, Hartmuth Daniel Kunze, Lothar E. Lehmann, Sven Bedürftig, Patrick Rohlfs
-
Publication number: 20220406732Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.Type: ApplicationFiled: June 21, 2021Publication date: December 22, 2022Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Nicholas A. Polomoff, Frank G. Kuechenmeister, Richard F. Taylor, III, Saquib B. Halim
-
Publication number: 20220308297Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) structure with a passage for a waveguide through a barrier structure. The PIC structure includes a barrier structure on a substrate, having a first sidewall and a second sidewall opposite the first sidewall. A passage is within the barrier structure, and extends from a first end at the first sidewall of the barrier structure to a second end at the second sidewall of the barrier structure. A shape of the passage includes a reversal segment between the first end and the second end. A waveguide within the passage and extends from the first end to the second end of the barrier structure.Type: ApplicationFiled: March 23, 2021Publication date: September 29, 2022Inventors: Nicholas A. Polomoff, John J. Ellis-Monaghan, Frank G. Kuechenmeister, Jae Kyu Cho, Michal Rakowski
-
Publication number: 20220238448Abstract: Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer.Type: ApplicationFiled: January 28, 2021Publication date: July 28, 2022Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Saquib B. Halim, Frank G. Kuechenmeister, Kashi V. Machani, Christian Goetze
-
Publication number: 20220237337Abstract: A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.Type: ApplicationFiled: January 26, 2021Publication date: July 28, 2022Applicant: GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KGInventors: Saquib B. Halim, Marcel B. Wieland, Frank G. Kuechenmeister
-
Publication number: 20220181271Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventors: Ranjan RAJOO, Frank G. KUECHENMEISTER, Dirk BREUER
-
Publication number: 20210280352Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. The IC structure may include a first metal layer on a substrate, and a second metal layer on the substrate that is horizontally separated from the first metal layer. A dielectric material may include a first portion on the first metal layer, and having a first upper surface, a second portion on the second metal layer, and having a second upper surface, and a third portion on the substrate between the first metal layer and the second metal layer. The third portion of the dielectric material includes a third upper surface above the first upper surface of the first portion and the second upper surface of the second portion of the dielectric material.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: Frank G. Küchenmeister, Marcel B. Wieland, Hartmuth Daniel Kunze, Lothar E. Lehmann, Sven Bedürftig, Patrick Rohlfs