Abstract: A dual purpose PCI-X DDR configurable terminator/driver providing programmable termination of the interface in a PCI-X system a plurality of N-channel devices divided into at least two groups and a plurality of P-channel devices also divided into at least two groups. A driver control individually controls selected ones of the groups of N-channel and P-channel devices on or off for providing internal termination to the transmission line. The configurable PCI-X DDR driver/terminator is configurable in three termination modes: pull-up mode, pull-down mode, and symmetric mode.

Abstract: A receiver with initial offset for biased idle transmission line suitable for providing a programmable amount of initial offset. The receiver comprises a standard differential receiver and one or more initial offset modules. Each initial offset module includes a transistor and two or more switches, which control the amount of offset to the differential receiver. A first switch receives a digital signal, which programs the amount of offset and a complementary digital signal is sent to a second switch to control the addition of the selected initial offset module(s).

Abstract: A the charge pump suitable for use in phase-locked loop (PLL) circuits employed by mixed signal integrated circuits (IC) is disclosed. The PLL charge pump includes a constant current source that generates constant current source references with high power supply rejection for the P- and N-channel devices of the charge pump. Pass-gate transistors are inserted between the output terminals and the drains of the respective P- and N-channel devices. The switching transients power supply and ground are confined to the turn on/off leads of the pass-gate transistors and, thus, are isolated from the constant current source P- and N-channel devices. In exemplary embodiments of the invention, the constant current of the P- and N-channel devices may be made programmable and used for controlling the range of the current controlled oscillator of the PLL circuit.

Abstract: The present invention allows a user to draw a closed periphery around an amount of information on the display of a pen-based computer system. The periphery information is transmitted to the computer system by a digitizing tablet. When received by the computer system, the computer system divides the area enclosed by the periphery into a number of lines. The computer system then processes each of these lines and determines the information to erase on a given line.

Abstract: A receiver with initial offset for biased idle transmission line suitable for providing a programmable amount of initial offset. The receiver comprises a standard differential receiver and one or more initial offset modules. Each initial offset module includes a transistor and two or more switches, which control the amount of offset to the differential receiver. A first switch receives a digital signal, which programs the amount of offset and a complementary digital signal is sent to a second switch to control the addition of the selected initial offset module(s).

Abstract: A method and apparatus for managing transmission of data signals in a plurality of data lines. Data signals are received on the data lines and a reference signal. On each of the data lines, a delay between the data signal and the reference signal is measured to form a plurality of delay measurements. A set of delay values from the delay measurements is generated. In a preferred embodiment of the present invention, the delay values are selected to equalize the delay in each of the data lines to have the same delay as the data line having the longest delay. The delay values are used to adjust delay in a transmission in each of the plurality of data signals in the data lines. In the preferred embodiment of the present invention, the reference signal is set such that transitions for the data signals are centered to the middle of a pulse for the reference signal.

Abstract: An equalization receiver responds to two differentially-related digital input signals occurring at a predetermined communication frequency. First and second input devices respond to the input signals and supply drive signals of a magnitude amplified relative to input signal by a factor related to the current conducted by the input devices. First and second current separate sources are connected to conduct current through the first and second input devices. An equalization circuit is connected between the first and second current sources. The equalization circuit has a frequency dependent impedance characteristic which exhibits a minimum impedance and a maximum coupling of the first and second current sources for the greatest current conductivity and the greatest amplification at the predetermined frequency.

Abstract: A dual purpose PCI-X DDR configurable terminator/driver providing programmable termination of the interface in a PCI-X system a plurality of N-channel devices divided into at least two groups and a plurality of P-channel devices also divided into at least two groups. A driver control individually controls selected ones of the groups of N-channel and P-channel devices on or off for providing internal termination to the transmission line. The configurable PCI-X DDR driver/terminator is configurable in three termination modes: pull-up mode, pull-down mode, and symmetric mode.

Abstract: A method and apparatus for a propagation delay and time calibration. The apparatus includes a ring oscillator having a first set of elements. The apparatus also includes delay units. The ring oscillator is used to generate a clock signal used to measure the delay in signals received at the delay blocks. In the depicted examples, the clock signal generated by the ring oscillator is used to run a counter that counts the delay between a transition in a data signal and a reference signal. Each of the delay units includes a second set of elements matching those of the first set of elements in the ring oscillator. The elements in the set of elements are selected such that they track the period of the ring oscillator signal generated by the ring oscillator. The delay units are used to implement the desired delay.

Abstract: A method of compensating for initial signal interference exhibited by a differential transmission line includes the step of determining whether the differential transmission line has been at a first differential voltage state for at least a first predetermined time period. The method also includes the step of transmitting a first data bit across the differential transmission line by impressing a first differential voltage having a first magnitude upon the differential voltage line in order to drive the differential transmission line from the first differential voltage state to a second differential voltage state if the determining step determines that the differential transmission line has not been at the first differential voltage state for at least the first predetermined time period.

Abstract: Process voltage temperature compensation are used for a bus driver; specifically, a PCI-X 2.0 DDR Standard bus driver. Performance is improved by enhancing the speed of the PCI-X buffer by removing the statically controlled gate stages and providing for output signal slew control by dual use of on-resistance of signal pass transistors. Although directed to PCI-X technology, this circuitry may also be used in SCCI, controlled impedance drivers, and other buffers, where short propagation delay and signal integrity are of concern.

Abstract: A the charge pump suitable for use in phase-locked loop (PLL) circuits employed by mixed signal integrated circuits (IC) is disclosed. The PLL charge pump includes a constant current source that generates constant current source references with high power supply rejection for the P- and N-channel devices of the charge pump. Pass-gate transistors are inserted between the output terminals and the drains of the respective P- and N-channel devices. The switching transients power supply and ground are confined to the turn on/off leads of the pass-gate transistors and, thus, are isolated from the constant current source P- and N-channel devices. In exemplary embodiments of the invention, the constant current of the P- and N-channel devices may be made programmable and used for controlling the range of the current controlled oscillator of the PLL circuit.

Abstract: Data signal pins for a peripheral device are adaptively precharged during hot plugging to a voltage level depending on both the mode of operation (low voltage differential, high voltage differential, or single ended) and the actual signal voltages being employed for a particular mode. An active terminator bus provides an operating mode sensing signal, from which the operating mode of the bus and the actual signal voltage levels being employed may be determined. Signal pins on an edge connector for the device are connected, in sequence, to the corresponding ground, power supply, operating mode sensing signal, and data signal conductors of the bus.

Abstract: Method and apparatus for voltage biasing a bus line are disclosed. In one embodiment, a terminator voltage biases a differential data line having a first bus line and a second bus line. The terminator, includes a resistor network, a biasing control circuit, and a controllable biasing circuit. The resistor network is coupled to the differential data line and has a network impedance substantially equal to the characteristic bus impedance of the differential data line. The controllable biasing circuit is coupled to the resistor network and is configured to generate (i) a first control signal and (ii) a second control signal. The controllable biasing circuit is coupled to the resistor network and to the biasing control circuit. The controllable biasing circuit is configured to generate a differential biasing voltage between the first bus line and the second bus line that is based on the first control signal and the second control signal.

Abstract: An integrated circuit chip controls a bus and terminates at least one differential data line of the bus wherein the at least one differential data line includes a first bus line of the bus and a second bus line of the bus. The integrated circuit chip includes a package and a substrate. The package includes terminals that are configured to couple the package to the bus. A first terminal is configured to couple the package to the first bus line, and a second terminal is configured to couple the package to the second bus line. The substrate is supported by the package. Furthermore, the substrate includes a bus controller circuit coupled to the terminals and a terminating circuit coupled to the first terminal and the second terminal. The bus controller circuit is configured to control transfer of data on the bus, and the terminating circuit is configured to substantially match a characteristic impedance of the at least one differential data line.

Abstract: Method and apparatus for transferring data on a voltage biased data line are disclosed. In one embodiment, there is provided a bus interface for controlling a differential bus having a differential data line that includes a first bus line and a second bus line. The bus interface includes a bus controller circuit, an impedance network, and a controllable biasing circuit. The bus controller circuit is coupled to the differential bus and is configured to (i) control transfer of data across the differential bus, and (ii) generate a biasing control signal prior to data transfer on the differential data line. The impedance network is coupled to the first bus line and the second bus line and is configured to substantially match a characteristic impedance of the differential data line.

Abstract: A differential receiver that includes a first input, a second input, and an output has a first signal path from the first input to the output, the first signal path including a first differential amplifier and a first active load. The first differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the first active load. The first differential amplifier also has a connection to the first input and the second input, and the first active load has a connection to the output. The receiver also has a second signal path from the second input to the output, the second signal path including a second differential amplifier and a second active load. The second differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the second active load.

Abstract: A bias current generator includes a first circuit component having a first voltage developed across a pair of terminals thereof, the first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component having a second voltage developed across a pair of terminals thereof, the second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator includes an impedance element connected to the first circuit component and the second component, the impedance element (1) having an impedance which increases as an operating temperature of the impedance element increases, and (2) having a first current flowing therethrough, wherein a decrease in the first voltage causes a corresponding increase in the first current, and a decrease in the second voltage causes a corresponding increase in the first current.

Abstract: The invention concerns pen-based computers, wherein a pen, or stylus, is positioned on a display of the computer, and produces a signal which allows the computer to detect the position of the stylus. The stylus produces a second signal, which is used as a carrier for telemetry, to transmit data from the stylus to the computer.

Abstract: A method and system for reducing pass-through current. The amount of simultaneous current flow through p-channel and n-channel devices of a CMOS inverter is reduced. This results in an increase in the power efficiency of CMOS oscillators, inverters, gates and other CMOS circuits. Another benefit of this invention is the increase of the output signal magnitude. This increase in the output signal with the lower power consumption yields a significantly higher efficiency of the CMOS circuit such as an oscillator.