Patents by Inventor Frank Goodwin

Frank Goodwin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8865376
    Abstract: Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 21, 2014
    Assignees: Sematech, Inc., Intel Corporation
    Inventors: Vibhu Jindal, Frank Goodwin, Patrick A. Kearney, Eric M. Panning
  • Publication number: 20140255828
    Abstract: Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicants: INTEL CORPORATION, SEMATECH, INC.
    Inventors: Vibhu JINDAL, Frank GOODWIN, Patrick A. KEARNEY, Eric M. PANNING
  • Patent number: 8173007
    Abstract: A system and method for the high temperature in-situ determination of corrosion characteristics of a molten metal on an alloy under study is provided which takes place within an insulated furnace. A graphite crucible provided in the furnace contains an electrolyte formed from a molten salt of a metal halide. A reference electrode formed from the same metal as the electrolyte is immersed in the electrolyte solution in the graphite crucible. A beta-alumina crucible containing a molten metal is also provided within the furnace and preferably within the graphite crucible. A measuring electrode formed from the alloy under study is immersed in the molten metal. Standard electrochemical techniques are used to measure and analyze the electrochemical effects of corrosion of the molten metal on the alloy.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: May 8, 2012
    Assignee: West Virginia University
    Inventors: Jing Xu, Xingbo Liu, Yinglu Jiang, Frank Goodwin
  • Publication number: 20090101522
    Abstract: A system and method for the high temperature in-situ determination of corrosion characteristics of a molten metal on an alloy under study is provided which takes place within an insulated furnace. A graphite crucible provided in the furnace contains an electrolyte formed from a molten salt of a metal halide. A reference electrode formed from the same metal as the electrolyte is immersed in the electrolyte solution in the graphite crucible. A beta-alumina crucible containing a molten metal is also provided within the furnace and preferably within the graphite crucible. A measuring electrode formed from the alloy under study is immersed in the molten metal. Standard electrochemical techniques are used to measure and analyze the electrochemical effects of corrosion of the molten metal on the alloy.
    Type: Application
    Filed: May 29, 2008
    Publication date: April 23, 2009
    Inventors: Jing Xu, Xingbo Liu, Yinglu Jiang, Frank Goodwin
  • Patent number: 7096127
    Abstract: Systems, methods, and lithography masks for measuring flare in semiconductor lithography. A layer of photosensitive material is exposed to a first test pattern and a second test pattern, the second test pattern comprising an opaque or attenuated region. The second test pattern is placed proximate features formed in a photosensitive material in a first exposure by the first test pattern, in a second exposure by the second test pattern on the same mask or a different mask. Alternatively, the second test pattern may be disposed proximate a portion of the first test pattern on a single mask using a single exposure. If flare exists in the optical system, the second test pattern causes line shortening in the features formed in the photosensitive material of the first test pattern. The line shortening can be measured to determine the effect of flare in the lithography system.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: August 22, 2006
    Assignee: Infineon Technologies AG
    Inventors: David Ziger, Ralf Ziebold, Frank Goodwin
  • Publication number: 20060080046
    Abstract: Systems, methods, and lithography masks for measuring flare in semiconductor lithography. A layer of photosensitive material is exposed to a first test pattern and a second test pattern, the second test pattern comprising an opaque or attenuated region. The second test pattern is placed proximate features formed in a photosensitive material in a first exposure by the first test pattern, in a second exposure by the second test pattern on the same mask or a different mask. Alternatively, the second test pattern may be disposed proximate a portion of the first test pattern on a single mask using a single exposure. If flare exists in the optical system, the second test pattern causes line shortening in the features formed in the photosensitive material of the first test pattern. The line shortening can be measured to determine the effect of flare in the lithography system.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 13, 2006
    Inventors: David Ziger, Ralf Ziebold, Frank Goodwin