Patents by Inventor Frank Grellner

Frank Grellner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6368902
    Abstract: Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable “blowing” of the fuse in the fuse region underlying the filler material. Since the “blow” area is predictable, damage to adjacent structures can be minimized or eliminated.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: April 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Frank Grellner, Sundar Kumar Iyer
  • Patent number: 6365512
    Abstract: A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack on a semiconductor substrate, and forming a protective layer on sidewalls of the gate stack. The protective layer extends horizontally over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer is formed over the protective layer and in contact with a gate conductor of the gate stack and in contact with a diffusion region formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: April 2, 2002
    Assignee: Infineon Technologies AG
    Inventors: Michael Stetter, Frank Grellner
  • Patent number: 6348419
    Abstract: A method for adjusting an etch rate of a nitride layer, in accordance with the present invention includes, in a reaction chamber, providing a surface for depositing a nitride layer. The nitride layer is deposited on the surface by adjusting processing parameters to control an etch rate achievable for the nitride layer. The etch rate achievable results from the depositing step such that an ability to etch the nitride layer is determined by the adjustment of the process parameters. A refractive index measurement may be provided for monitoring the achievable etch rate for the nitride layer.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: February 19, 2002
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Frank Grellner, Paul C. Jamison, Glen L. Miles, David C. Mosher, Emmanuel Batt