Abstract: Some embodiments of the invention provide a method for a first security controller that performs security operations on the packets that are transmitted within a network. The method of some embodiments receives a packet from a forwarding element in the network based on a decision made by a security agent that operates along with the forwarding element. When the first security controller stores a security rule for the packet, the method processes the packet according to the stored security rule. When the first security controller does not store a security rule for the packet, the method (i) determines that a second security controller stores a security rule for the packet based on a set of header values of the packet, and (ii) sends the packet to the second security controller for security processing according to the security rule for the packet stored on the second security controller.

Abstract: This application relates generally to logging information, and more particularly to techniques for configuring a software product to have each log call in source code controllable at runtime. The source code can be preprocessed so that individual log calls in the source code can be identified and tracked. Information specifying locations of the log calls can be used to generate a bitmap indicating whether to write log messages (corresponding to the log calls) to a log file. The preprocessed source code can then be compiled into executable code, which can be packaged with the bitmap into an executable product such that the executable code can run based on the bitmap. While the executable code is executing, examples described herein can also allow the bitmap to be updated, allowing control during execution.

Abstract: This invention relates to thyristor memory cells with MOS assist gates for enhanced operations. This invention solves various disturb problems in cross point memory array using the thyristor memory cells, including the techniques for protecting stored data inside unselected and half selected bit cells, for recovering weakened stored data in disturbed bit cells, and for effectively shutting off bit cells with minimum disturbance.

Abstract: Aspects of the present disclosure provide a method for processing address resolution protocol (ARP) packets in a computing environment. The method includes the steps of maintaining a table mapping internet protocol (IP) addresses to port identifiers (port IDs), receiving a packet, determining a type of the received packet, based on the type of the received packet being a first type, checking whether a destination IP address in the received packet matches an entry in the table, and if the destination IP address in the received packet matches an entry in the table: determining a port ID associated with the matching entry, and forwarding the received packet over a port associated with the determined port ID.

Abstract: Some embodiments of the invention provide a method for a first security controller that performs security operations on the packets that are transmitted within a network. The method of some embodiments receives a packet from a forwarding element in the network based on a decision made by a security agent that operates along with the forwarding element. When the first security controller stores a security rule for the packet, the method processes the packet according to the stored security rule. When the first security controller does not store a security rule for the packet, the method (i) determines that a second security controller stores a security rule for the packet based on a set of header values of the packet, and (ii) sends the packet to the second security controller for security processing according to the security rule for the packet stored on the second security controller.

Abstract: Some embodiments of the invention provide a method for a first security controller that performs security operations on the packets that are transmitted within a network. The method of some embodiments receives a packet from a forwarding element in the network based on a decision made by a security agent that operates along with the forwarding element. When the first security controller stores a security rule for the packet, the method processes the packet according to the stored security rule. When the first security controller does not store a security rule for the packet, the method (i) determines that a second security controller stores a security rule for the packet based on a set of header values of the packet, and (ii) sends the packet to the second security controller for security processing according to the security rule for the packet stored on the second security controller.

Abstract: This invention relates to thyristor memory cells with MOS assist gates for enhanced operations. This invention solves various disturb problems in cross point memory array using the thyristor memory cells, including the techniques for protecting stored data inside unselected and half selected bit cells, for recovering weakened stored data in disturbed bit cells, and for effectively shutting off bit cells with minimum disturbance.

Abstract: Aspects of the present disclosure provide a method for processing address resolution protocol (ARP) packets in a computing environment. The method includes the steps of maintaining a table mapping internet protocol (IP) addresses to port identifiers (port IDs), receiving a packet, determining a type of the received packet, based on the type of the received packet being a first type, checking whether a destination IP address in the received packet matches an entry in the table, and if the destination IP address in the received packet matches an entry in the table: determining a port ID associated with the matching entry, and forwarding the received packet over a port associated with the determined port ID.

Abstract: Some embodiments of the invention provide a method that performs security operations for packets that are processed by a forwarding element. The method of some embodiments receives, at a security agent operating on a physical machine, a packet from a forwarding element that also operates on the physical machine. The method then determines whether a security rule is stored for the packet at the security agent. When no security rule is stored for the packet, the method transmits the packet to a default security controller of several security controllers that store security rules for a network and process packets according to the stored security rules. When the security rule is stored for the packet, the method processes the packet according to the stored security rule for the packet.

Abstract: Techniques are provided for managing voltages on memory cells in a cross-point array during a read operation. The techniques apply to vertical layer thyristor memory cells and non-thyristor memory cells. Voltages on selected bitlines (e.g., corresponding to memory cells from which data is to be read), are set to a read voltage level. Voltages on unselected bitlines (e.g., corresponding to memory cells from which data is not to be read and which are not to be disturbed) are set to a de-bias voltage level that is different from the read voltage level.

Abstract: Techniques are provided for managing voltages applied to memory cells in a cross-point array during a write operation (e.g., to transition from a resistive state into a conductive state). The techniques apply to thyristor memory cells and non-thyristor memory cells. Bitlines, connected by a wordline, are preconditioned to a voltage level, by a precondition device, to write data to one or more memory cells at intersections of the bitlines and the wordline. Each bitline is coupled to a high impedance device, a detect device, a precondition device and a clamp device. When a memory cell on a first bitline transitions from a resistive state into a conductive state, it pulls a voltage level of the first-bit line level low. A first clamp device maintains the voltage level at a level to de-bias the first bitline from the wordline, while other memory cells to be written along the wordline remain biased.

Abstract: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.

Abstract: Some embodiments of the invention provide a method that performs security operations for packets that are processed by a forwarding element. The method of some embodiments receives, at a security agent operating on a physical machine, a packet from a forwarding element that also operates on the physical machine. The method then determines whether a security rule is stored for the packet at the security agent. When no security rule is stored for the packet, the method transmits the packet to a default security controller of several security controllers that store security rules for a network and process packets according to the stored security rules. When the security rule is stored for the packet, the method processes the packet according to the stored security rule for the packet.

Abstract: Some embodiments of the invention provide a method for a first security controller that performs security operations on the packets that are transmitted within a network. The method of some embodiments receives a packet from a forwarding element in the network based on a decision made by a security agent that operates along with the forwarding element. When the first security controller stores a security rule for the packet, the method processes the packet according to the stored security rule. When the first security controller does not store a security rule for the packet, the method (i) determines that a second security controller stores a security rule for the packet based on a set of header values of the packet, and (ii) sends the packet to the second security controller for security processing according to the security rule for the packet stored on the second security controller.

Abstract: A level-shifter is provided with PMOS stacks that are selectively weakened or strengthened depending upon the binary state of an input signal.

Abstract: A level-shifter is provided with PMOS stacks that are selectively weakened or strengthened depending upon the binary state of an input signal.

Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

Abstract: An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.

Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

Abstract: An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.