Abstract: An arrangement is described for scrambling data streams having arbitrary data path widths. The arrangement includes logic configured to generate a maximal length pseudorandom sequence of digital signals. A first register is configured to store the pseudorandom sequence. Logic, coupled to the first register, is configured to combine a portion of the pseudorandom sequence with a corresponding portion of an input data stream to produce a scrambled data word. A second register is configured to store the scrambled data word. Circuitry is configured to circularly shift the pseudorandom sequence a number of bits forming the portion of the pseudorandom sequence used to produce the scrambled data word.