Abstract: A method of fabricating gallium arsenide devices in which contact isolation is provided by a deep mesa step structure. Step coverage of deposited conductive films is facilitated by preferential orientation of the non-centrosymmetric crystal substrate and wet anisotropic etching that provides a sloped step. Problems of fine line definition of the Schottky anode contact in the photolithographic process are addressed by a two-step exposure of a single layer of thick photoresist followed by a chlorobenzene soak prior to development that ensures a retrograde resist profile needed for good lift-off of undesired evaporated metal. Mesas as deep as 7 .mu.m have been obtained, which permit the fabrication of monolithic planar mixer millimeter-wave diodes with low series resistance and reduced parasitic capacitance.

Abstract: A method of fabricating semiconductor devices on semi-insulating GaAs substrates is provided. Pre-etched holes in the substrate are covered with a dielectric which is etched to expose the substrate only at the bottom of the holes. Epitaxial growth of active GaAs in the holes may then proceed with a single crystallographic orientation. The dielectric covering the sidewalls of the holes prevents unwanted random growth and poor surface morphology of the active area.

Abstract: A method of fabricating gallium arsenide circuits or devices in which source and drain contact areas are deposited using vapor phase epitaxy techniques through holes in a refractory mask. Selected areas of a refractory mask are etched away to expose a region of active gallium arsenide material in which holes are formed by a chemical or plasma etch. These holes are then filled with highly doped vapor phase epitaxially grown gallium arsenide to provide drain and source contact regions. In further steps additional regions of the refractory mask are etched away to define gate regions. Metallization and lift-off may then occur in a single step to provide contacts to gate, drain and source regions and a planar surface for further device processing.

Abstract: A temperature compensated surface acoustic wave device having an SiO.sub.2 film layer upon a substrate of piezoelectric material. The positive temperature coefficient of delay of the piezoelectric substrate is counterbalanced by the negative temperature coefficient of the SiO.sub.2 layer. The thickness and shape of the SiO.sub.2 layer are chosen to give a zero first order temperature coefficient for the composite device. Lithium niobate and lithium tantalate are preferred piezoelectric materials for the substrate. A high degree of temperature stability is thereby obtained with coupling coefficients much greater than were previously obtained by prior temperature compensated surface acoustic wave devices.