Patents by Inventor Frank Hady

Frank Hady has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060112235
    Abstract: In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specifying an access to data.
    Type: Application
    Filed: November 19, 2004
    Publication date: May 25, 2006
    Inventors: Mason Cabot, Frank Hady, Mark Rosenbluth
  • Publication number: 20060069838
    Abstract: A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An additional agent may monitor the symmetric arbitration of the symmetric agents, and at a given stage of the symmetric arbitration assert a priority agent bus request. The priority agent bus request may be shared with another priority agent. This may permit the additional agent to access the bus in a fair manner that behaves as though it were an additional symmetric agent in the system.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 30, 2006
    Inventors: Mason Cabot, Frank Hady, John Beck
  • Publication number: 20050216667
    Abstract: A method, apparatus, and system for implementing off-chip cache memory in dual-use static random access memory (SRAM) memory for network processors. An off-chip SRAM memory store is partitioned into a resizable cache region and general-purpose use region (i.e., conventional SRAM use). The cache region is used to store cached data corresponding to portions of data contained in a second off-chip memory store, such as a dynamic RAM (DRAM) memory store or an alternative type of memory store, such as a Rambus DRAM (RDRAM) memory store. An on-chip cache management controller is integrated on the network processor. Various cache management schemes are disclosed, including hardware-based cache tag arrays, memory-based cache tag arrays, content-addressable memory (CAM)-based cache management, and memory address-to-cache line lookup schemes. Under one scheme, multiple network processors are enabled to access shared SRAM and shared DRAM, wherein a portion of the shared SRAM is used as a cache for the shared DRAM.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 29, 2005
    Inventors: Mason Cabot, Frank Hady, Mark Rosenbluth
  • Publication number: 20030083849
    Abstract: A method of sampling data includes gathering a first data sample during execution of a program, executing the program during a random inter-sample period and gathering a second data sample following the inter-sample period. The method may also include generating an inter-sample count and decrementing the inter-sample count to zero before gathering the second data sample.
    Type: Application
    Filed: October 31, 2001
    Publication date: May 1, 2003
    Inventors: Mason B. Cabot, Frank Hady