Abstract: A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Abstract: A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.

Abstract: A metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. An insulating layer is disposed above a lower metal interconnect layer. The insulating layer includes a via formed therethrough containing a tungsten plug in electrical contact with the lower metal interconnect layer. An antifuse material layer comprising amorphous carbon is disposed above the upper surface of the tungsten plug. The antifuse material layer is disposed between adhesion-promoting layers. A layer of a barrier metal, consisting of either tantalum or tantalum nitride, is disposed over the antifuse layer to form an upper electrode of the antifuse. An oxide or tungsten hard mask provides high etch selectivity and the possibility to etch barrier metals without affecting the dielectric constant value and mechanical properties of the antifuse.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Abstract: A method for fabricating a shallow-trench isolation transistor an a semi-conductor substrate includes forming a single isolation trench having a uniform cross section to define an active region in the silicon substrate. The method includes performing sidewall isolation implants on the side and bottom walls of said isolation trench. The method includes depositing a dielectric isolation material in said isolation trench. The method includes planarizing the top surface of said silicon substrate and said dielectric isolation material. The method includes forming a gate oxide layer over said active region in said silicon substrate. The method includes forming and defining gate regions over said oxide layer in said active region in said silicon substrate. The method includes forming source and drain regions in the active region in the silicon substrate.

Abstract: A shallow-trench isolation includes a semiconductor substrate. Spaced apart source and drain regions define an active region in the semiconductor substrate. A single isolation trench is in the semiconductor substrate having a uniform cross-section surrounds the active region. An isolation implant is formed in the sidewalls of the isolation trench. A gate dielectric layer is formed over the active region. A gate is disposed over the gate dielectric layer and is located between the source and drain region.

Abstract: A method of fabricating a metal-to-metal antifuse, comprising planarizing an insulating layer and a tungsten plug, forming an antifuse material layer over the insulating layer and the tungsten plug, defining the antifuse material layer, forming a barrier metal layer over the antifuse material layer, defining the barrier metal layer, forming an oxide or tungsten layer over the barrier metal layer, forming a layer of photoresist over the oxide or the tungsten layer, defining the oxide or the tungsten layer, removing the photoresist, forming a first masking layer over the barrier metal layer, defining a shape of the antifuse, removing the first masking layer, forming a metal interconnect layer over the insulating layer, forming a second masking layer over the metal interconnect layer, and removing the second masking layer.

Abstract: In a first embodiment, programming pulses of about 0.25 mA to about 0.5 mA are applied to an amorphous carbon based antifuse in first and second directions for 10 us to form an antifuse link having a finite resistance of less than 2000 ohms. Soaking pulses of about 2 mA to about 5 mA are then applied to the amorphous carbon antifuse in first and second directions for 1 ms and then repeated up to four more times to form an antifuse link with a finite resistance of about 100 ohms to about 400 ohms. In a second embodiment, programming pulses of about 0.25 mA to about 0.5 mA are applied to an amorphous carbon based antifuse in first and second directions for 1 ms and then repeated four more times to form an antifuse link having a finite resistance of less than 2000 ohms.

Abstract: A metal-to-metal antifuse according to the present invention is disposed between a lower conductive electrode and an upper conductive electrode. The conductive electrodes may comprise either a barrier metal or a tungsten plug, and are each in electrical contact with a metal layer, usually a metal interconnect layer in an integrated circuit. An antifuse material is disposed between the lower and upper conductive electrodes and comprises a layer of amorphous silicon. The antifuse layer is sandwiched between two layers of silicon nitride.

Abstract: A metal-to-metal antifuse according to the present invention is disposed between a lower conductive electrode and an upper conductive electrode. The conductive electrodes may comprise either a barrier metal or a tungsten plug, and are each in electrical contact with a metal layer, usually a metal interconnect layer in an integrated circuit. An antifuse material is disposed between the lower and upper conductive electrodes and comprises a layer of amorphous silicon. The antifuse layer is sandwiched between two layers of silicon nitride.

Abstract: An apparatus for automatically controlling the activation of the throttle on a carburetor on the engine of a drag race car before the start of the race while staging the car. The apparatus eliminates some of the tasks a driver must perform during the process of staging and launching a race vehicle on the starting line(such as physically depressing the throttle pedal) using a starting line throttle actuation system for Pro tree and Full tree modes for controlling the throttle opening. In both Pro and Full tree modes, the staging process is simplified by allowing the driver to stage with the throttle pedal pre-depressed in the wide open down position, with the actual opening of the throttle controlled by the starting line throttle actuation control system. The apparatus has the driver use the same staging procedure for both Pro tree and Full tree races, thus eliminating separate training that has been required for Pro and Full tree races.

Abstract: An adjustable automatic starting line throttle actuation controller for use with a drag racing vehicle. The device controls the throttle from a preset partial throttle opening to a wide open throttle during the initial staging process of the race, while the driver holds the throttle in a wide open position. The device can control the opening of the carburetor linkage of the carburetor to a preset low r.p.m. at the starting line (during the staging process) before a race begins, and control the opening of the throttle for the first portion of the race after the race starts. A preferred version of the device has a dual piston cylinder having respective piston rods connected to the carburetor and one connected to the throttle pedal. An electronic activation assembly controls which piston rod is being actuated.