Abstract: A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

Abstract: An integrated circuit including a capacitor and a method of fabricating an integrated circuit. The capacitor has a first electrode. A plurality of conductive lines is separated from each other and is configured to be held at a potential being the same for all conductive lines. A second electrode encloses individual ones of the conductive lines at a top side and at least one lateral side and is separated from the first electrode by a dielectric layer. The second electrode includes a polycrystalline semiconductor material, a metal or a metal-semiconductor compound.

Abstract: A semiconductor memory device includes a semiconductor substrate, first conductive lines, second conductive lines, and memory cells. The second conductive lines include doped regions within the substrate and have a ratio of depth to width that is greater than unity. A semiconductor structure comprises a semiconductor substrate, a doped region and a charge trapping region beneath and adjoining the doped region. A semiconductor memory device comprises a semiconductor substrate, first conductive lines, second conductive lines, charge trapping regions, and memory cells. The second conductive lines are formed as doped regions within the substrate, wherein the charge trapping regions are arranged beneath and adjoin respective doped regions. Methods of manufacturing a semiconductor structure and a semiconductor memory device are provided.