Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Abstract: According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode.

Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Abstract: The disclosure is directed to a semiconductor wafer, integrated circuit product, and method of making same, having multiple non-singulated chips separated by scribe lines, comprising a plurality of seal rings, each seal ring surrounding a corresponding chip and disposed between the corresponding chip and adjacent scribe lines. Well resistors are disposed below the seal rings and probe pads disposed in the scribe lines. In particular, at least one of the probe pads is coupled by at least one of the well resistors to at least one of the chips.

Abstract: According to one embodiment, a one-time programmable (OTP) semiconductor device includes a programming dielectric under a patterned electrode and over an implant region, where the programming dielectric forms a programming region of the OTP semiconductor device. The OTP semiconductor device further includes an isolation region laterally separating the programming dielectric from a coupled semiconductor structure, where the isolation region can be used in conjunction with the patterned electrode and the implant region to protect the coupled semiconductor structure. In one embodiment, the programming dielectric comprises a gate dielectric. In another embodiment, the electrode and implant regions are doped to be electrochemically similar.

Abstract: According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Abstract: According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin.

Abstract: According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Abstract: According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode.

Abstract: According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin.

Abstract: According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: The disclosure is directed to a semiconductor wafer, integrated circuit product, and method of making same, having multiple non-singulated chips separated by scribe lines, comprising a plurality of seal rings, each seal ring surrounding a corresponding chip and disposed between the corresponding chip and adjacent scribe lines. Well resistors are disposed below the seal rings and probe pads disposed in the scribe lines. In particular, at least one of the probe pads is coupled by at least one of the well resistors to at least one of the chips.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: According to one embodiment, a one-time programmable (OTP) semiconductor device includes a programming dielectric under a patterned electrode and over an implant region, where the programming dielectric forms a programming region of the OTP semiconductor device. The OTP semiconductor device further includes an isolation region laterally separating the programming dielectric from a coupled semiconductor structure, where the isolation region can be used in conjunction with the patterned electrode and the implant region to protect the coupled semiconductor structure. In one embodiment, the programming dielectric comprises a gate dielectric. In another embodiment, the electrode and implant regions are doped to be electrochemically similar.