Abstract: Reliability of circuit packaging while accommodating larger chips and increased temperature excursions is achieved by use of compliant pads only at the locations of connections between packaging levels, preferably between a laminated chip carrier and a printed circuit board. The invention allows the coefficient of thermal expansion of the chip carrier to be economically well-matched to the CTE of the chip and accommodation of significant differences in CTEs of package materials to be accommodated at a single packaging level. The compliant pads are preferably of low aspect ratio which are not significantly deflected by accelerations and can be formed on a surface or recessed into it. Connections can be made through surface connections and/or plated through holes. Connection enhancements such as solder wettable surfaces or dendritic textures are provided in a conductive metal or alloy layer over a compliant rubber or elastomer layer which may be conductive or non-conductive.