Abstract: The present disclosure is directed, in part, to a method for fabricating a low-stress, ultra-thin membrane as well as the low-stress, ultra-thin membrane formed by this method. The method includes: layering a first layer on a semiconductor substrate; etching a hole in the first layer; layering a second layer on the membrane of the first layer and over the hole; and etching the substrate beginning from the bottom surface thereof, such that at least a portion of the substrate aligned with the hole in the first layer is removed. The first and second layers are made of substantially the same material, which will usually be silicon nitride, however, it is contemplated that other dielectric materials could be used, but it is preferred that the second layer has an amorphous structure. It is preferred that the second layer be formed with a slightly bubble-shape to help deflect stresses on the second layer. Generally, low pressure chemical vapor deposition will be used to create at least the first and second layers.

Abstract: A vacuum window transmitting keV electrons and usable for high-pressure electron analysis such as XPS and AES in which the sample is positioned outside the UHV analyzer chamber, possibly in a controlled gas environment, relatively close to the window. The window includes a grid formed from a support layer and a thin window layer supported between the ribs and having a thickness preferably of 2 to 3 nm. The window and support layers may be deposited on a silicon wafer and the support layer is lithographically defined into the grid. The wafer is backside etched to expose the back of the grid and its supported window layer. Such a window enables compact and easily used electron analyzers and further allows control of the gas environment at the sample surface during analysis.

Abstract: An energy filter for charged particles includes a stack of micro-machined wafers including plural apertures passing through the stack of wafers, focusing electrodes bounding charged particle paths through the apertures, an entrance orifice to each of the plural apertures and an exit orifice from each of the plural apertures and apparatus for biasing the focusing electrodes with an electrostatic potential corresponding to an energy pass band of the filter.

Abstract: A process for fabricating gold/gallium arsenide structures, in situ, on molecular beam epitaxially grown gallium arsenide. The resulting interface proves to be Ohmic, an unexpected result which is interpreted in terms of increased electrode interdiffusion. More importantly, the present invention surprisingly permits the fabrication of Ohmic contacts in a III-V semiconductor material at room temperature. Although it may be desireable to heat the Ohmic contact to a temperature of, for example, 200 degrees Centigrade if one wishes to further decrease the resistance of the contact, such low temperature annealing is much less likely to have any deleterious affect on the underlying substrate. The use of the term "in situ" herein, contemplates continuously maintaining an ultra-high vacuum, that is a vacuum which is at least 10.sup.-8 Torr, until after the metallization has been completed.

Abstract: The backside surface potential well of a backside-illuminated CCD is confined to within about half a nanometer of the surface by using molecular beam epitaxy (MBE) to grow a delta-doped silicon layer on the back surface. Delta-doping in an MBE process is achieved by temporarily interrupting the evaporated silicon source during MBE growth without interrupting the evaporated p+ dopant source (e.g., boron). This produces an extremely sharp dopant profile in which the dopant is confined to only a few atomic layers, creating an electric field high enough to confine the backside surface potential well to within half a nanometer of the surface. Because the probability of UV-generated electrons being trapped by such a narrow potential well is low, the internal quantum efficiency of the CCD is nearly 100% throughout the UV wavelength range. Furthermore, the quantum efficiency is quite stable.

Abstract: The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip.

Abstract: A process for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface of the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Abstract: For the growth of strain-layer materials and high quality single and multiple quantum wells, the instantaneous control of growth front stoichiometry is critical. The process of the invention adjusts the offset or phase of MBE control shutters to program the instantaneous arrival or flux rate of In and As.sub.4 reactants to grow InAs. The interrupted growth of first In, then As.sub.4, is also a key feature.

Abstract: III-V films are grown on large automatically perfect terraces of III-V substrates which have a different lattice constant, with temperature and Group II and V arrival rates chosen to give a Group III element stable surface. The growth is pulsed to inhibit Group III metal accumulation to low temperature, and to permit the film to relax to equilibrium. The method of the invention 1) minimizes starting step density on sample surface; 2) deposits InAs and GaAs using an interrupted growth mode (0.25 to 2 mono-layers at a time); 3) maintains the instantaneous surface stoichiometry during growth (As-stable for GaAs, In-stable for InAs); and 4) uses time-resolved RHEED to achieve aspects (1)-14 (3).

Abstract: An improved X-ray photoelectron spectrometer is disclosed, which includes circuit means to determine the surface potential of a sample, e.g., an insulator. The circuit means comprise an electron gun, whose potential is modulated at a preselected frequency above and below a selected potential with respect to the spectrometer common potential, e.g., ground. The beam of electrons is directed to the sample surface. The sample's surface potential is offset by an offset power supply with respect to the spectrometer common potential until the AC current which flows through the sample reaches a peak amplitude. A lock-in amplifier is included to measure the AC current in phase with the modulating frequency.