Abstract: A static read-only-memory (ROM) is derived from a gate array in which both P-channel transistor (24) and an N-channel transistor (30) are used to convey a logic 1 or 0 to a bitline (Bitline0). The invention maximizes the use of gate array transistors in a gate-array chip and achieves a high density of ROM bits per unit area. In CMOS gate arrays, transistors are arrayed in alternating rows of P-channel and N-channel transistors. A decoding scheme inverts the logic signal to each row of P-channel transistors to yield a functional ROM.

Abstract: A BICMOS latch driver L/D is used to implement a BICMOS gate array memory cell (FIG. 2b). The memory cell includes a latch formed by cross-coupled invertors (INV1 and INV2). The driver stage is formed by an NPN transistor Q0 and an n-channel transistor MN3. The relatively stronger bipolar transistor is used to pull the output of the BICMOS latch/driver HI, while, for most applications, the relatively weaker n-channel device has sufficient strength to pull the output low. A WRITE port (WP) that interfaces to the WRITE bitline, and a READ port (RP) that interfaces to the READ bitline.