Abstract: Probecard architectures partition the spring compliance required for IC testing between several different components. Such architectures can provide shorter springs, better impedance control, improved power/ground distribution and more direct paths to tester electronics. The probecards can also use thinner interconnector substrates to conform to the planarity of a DUT and may suspend such a substrate by wires attached to a perimeter edge of the substrate to permit the substrate to tilt. Tilting can also be facilitated by positioning tester-side springs away from the perimeter of the substrate. Low compliance MEMS probes for such architectures can be provided on replaceable coupons having attachment points away from electrical connections, and a method for fabricating probe springs can plate spring material on a membrane deformed by contact with a bumped substrate.

Abstract: Processes are described for building low compliance MEMS type C-spring probes in a coupon form that can be used as replaceable probes in probe card applications. The coupons have plated spring structures and a plated frame that holds a thin polyimide film in tension. The film keeps the probes and their tips of the top probes aligned to the pads of an IC being tested and the probes and tips of bottom probes aligned to the pads of a probe card high density interconnect that routes to an IC tester.

Abstract: A high speed multiplier array implemented with a current switch emitter follower logic gate employs an inverted carry signal internal to the array. External carry signals received by the array are first inverted for internal processing. This implementation eliminates the necessity of employing a buffer gate between subarray integrated circuit chips or cells and thus decreases propagation delays in the overall array.

Abstract: A current mode logic circuit providing AND/OR type functions wherein "0" voltage level changes and spikes are substantially eliminated without sacrificing switching speeds by omitting conventional emitter and collector-dotting between the logic input gates and an emitter-follower output stage. The input gates employ diode loads for generating reduced signal swings for driving the output gate. The output gate contains more devices than a single emitter-follower output stage, but the reduced signal swing and a push-pull drive mode for the output gate offsets any increased switching times due to the greater number of devices and thus achieves the overall objectives without any overall sacrifice in switching speed.