Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to pressure sensors and methods of manufacture. The structure includes: a top membrane of semiconductor material having edges defined by epitaxial material and a liner material; a back gate under the top membrane; and a cavity defined between the top membrane and the back gate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to pressure sensors and methods of manufacture. The structure includes: a top membrane of semiconductor material having edges defined by epitaxial material and a liner material; a back gate under the top membrane; and a cavity defined between the top membrane and the back gate.

Abstract: A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings.

Abstract: A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings.

Abstract: A semiconductor structure includes a support substrate including a semiconductor material, a buried insulation layer positioned above the support substrate, a semiconductor layer positioned above the buried insulation layer, the semiconductor layer having an upper surface and a lower surface, the lower surface being positioned on the buried insulation layer, and at least one nonvolatile memory cell. The nonvolatile memory cell includes a channel region, a front gate structure, a doped back gate region and a charge storage material. The channel region is located in the semiconductor layer. The front gate structure is located above the channel region and the upper surface of the semiconductor layer. The doped back gate region is located in the support substrate below the channel region. The charge storage material is embedded at least into a portion of the buried insulation layer between the channel region and the back gate region.

Abstract: The present disclosure provides semiconductor devices and manufacturing techniques in which a buried capacitive structure may be provided at the level of the buried insulating layer of an SOI device, thereby providing reduced process complexity compared to conventional strategies, while still preserving superior routing capabilities above the buried capacitive structures.

Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Abstract: A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions.

Abstract: Integrated circuits employing replacement metal gate technologies with separate workfunction material layers and raised source/drain structures and methods for fabricating the same are disclosed herein. In one exemplary embodiment, a method of fabricating an integrated circuit includes forming a first workfunction material layer over an ILD layer, along the sidewall spacer structures, and over the high-k material layer. The method further includes forming a masking layer over the first workfunction material layer, performing a tilted ion implant wherein ions are implanted at the masking layer over the ILD layer and along the sidewall spacer structures, selectively etching the masking layer and the first workfunction material from over the ILD layer and from along the sidewall spacer structures, and forming a second workfunction material layer over the ILD layer, along the sidewall spacer structures, and over the first workfunction material layer.

Abstract: A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width WT defined by outer and inner rings of the protection unit. The substrate is etched to form at least a trench in the second region of the substrate. The WT of the protection unit is sufficiently wide to protect the first region of the wafer substrate such that the first region is devoid of trench.

Abstract: An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively.

Abstract: A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region.

Abstract: A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region.

Abstract: Disclosed are methods of forming bulk FinFET semiconductor devices to reduce punch through leakage currents. One example includes forming a plurality of trenches in a semiconducting substrate to define a plurality of spaced-apart fins, forming a doped layer of insulating material in the trenches, wherein an exposed portion of each of the fins extends above an upper surface of the doped layer of insulating material while a covered portion of each of the fins is positioned below the upper surface of the doped layer of insulating material, and performing a process operation to heat at least the doped layer of insulating material to cause a dopant material in the doped layer to migrate from the doped layer of insulating material into the covered portions of the fins and thereby define a doped region in the covered portions of the fins that is positioned under the exposed portions of the fins.

Abstract: In aspects of the present disclosure, a reliable encapsulation of a gate dielectric is provided at very early stages during fabrication. In other aspects, a semiconductor device is provided wherein a reliable encapsulation of a gate dielectric material is maintained, the reliable encapsulation being present at early stages during fabrication. In embodiments, a semiconductor device having a plurality of gate structures is provided over a surface of a semiconductor substrate. Sidewall spacers are formed over the surface and adjacent to each of the plurality of gate structures, wherein the sidewall spacers cover sidewall surfaces of each of the plurality of gate structures.

Abstract: One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region.

Abstract: A method of forming a conductive contact landing pad and a transistor includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, and performing an etching process to remove the layer of gate insulation material formed on the second active region so as to thereby expose the second active region. The method further includes performing a common process operation to form a gate electrode structure above the layer of gate insulation material on the first active region for the transistor and the conductive contact landing pad that is conductively coupled to the second active region, and forming a contact to the conductive contact landing pad.