Abstract: The present disclosure relates to a packaging process using a low pressure encapsulant. According to an exemplary process, an assembly including a substrate, a surface mounted device (SMD) mounted on the substrate, and a space between the SMD and the substrate is provided. The SMD has a sealed cavity biased towards the substrate. A sheet mold compound is laid over the SMD and the assembly is heated such that the sheet mold compound transitions to a liquid phase to form a molten mold compound. Next, the assembly is subjected to a vacuum that creates a negative atmosphere allowing the molten mold compound to flow towards the top surface of the substrate and about the SMD. The molten mold compound is then pressed towards the substrate at a low pressure (<=2 Mpa) such that the space between the SMD and the substrate is substantially filled and the SMD is substantially encapsulated.

Abstract: The present disclosure relates to a packaging process using a low pressure encapsulant. According to an exemplary process, an assembly including a substrate, a surface mounted device (SMD) mounted on the substrate, and a space between the SMD and the substrate is provided. The SMD has a sealed cavity biased towards the substrate. A sheet mold compound is laid over the SMD and the assembly is heated such that the sheet mold compound transitions to a liquid phase to form a molten mold compound. Next, the assembly is subjected to a vacuum that creates a negative atmosphere allowing the molten mold compound to flow towards the top surface of the substrate and about the SMD. The molten mold compound is then pressed towards the substrate at a low pressure (<=2 Mpa) such that the space between the SMD and the substrate is substantially filled and the SMD is substantially encapsulated.

Abstract: Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having an active surface, a conductive pillar formed on the active surface of the die, the conductive pillar having a side surface, and a molding material encasing the die and the conductive pillar, including covering the active surface of the die and the side surface of the conductive pillar. Methods for making the same also are described.

Abstract: A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (100) including a lead frame (10) having a plurality of leads (11) each having a down set portion (101) extending from a first surface (14). A semiconductor die (30) is disposed in a central region (12) of the lead frame (10) and is electrically connected to the leads (11). An encapsulant (50) is disposed in the central region (12) and covers to the semiconductor die (30) and a portion of the leads (11). The first surface (14) of the leads (11) and a first surface (34) of the semiconductor die (30) are substantially coplanar and are exposed from the encapsulant (50). The first surface (34) of the semiconductor die (30) and the down set portions (101) of the leads form a cavity (102).

Abstract: A package includes both a flip chip mounted active chip component and a passive chip component. To form the package, a solder paste is screened onto a passive chip component contact on an upper surface of a substrate. A terminal of the passive chip component is aligned with the solder paste. The solder paste is melted to form a solder joint between the passive chip component contact and the terminal. Solder flux residue from the solder paste is removed. A solder bump is formed on a bond pad of an active chip component. The solder bump is aligned with an active chip component contact on the upper surface of the substrate. The solder bump is melted to form a bump between the active chip component contact and the bond pad, wherein the solder joint does not melt during the melting of the solder bump.

Abstract: A method for overmolding a ceramic substrate for a semiconductor chip or other electrical device, and a resulting package, are disclosed. In one embodiment, plural ceramic substrate panels having a matrix of semiconductor chips thereon are precisely located on and attached to a temporary support member using an alignment tool. The member and the attached ceramic substrate panels are then placed in a mold tool. When the mold tool is closed, it clamps down on the member around the ceramic substrate panel, and not on the ceramic substrate panel itself. A mold compound injected into the mold tool encapsulates the chips and ceramic substrate panels. Subsequently, packages each containing a chip are singulated from the encapsulated ceramic substrate panels.

Abstract: A package includes both a flip chip mounted active Chip component and a passive chip component. The flip chip bumps between the bond pads of the active chip component and the substrate are low impedance. Further, by mounting the active chip component as a flip chip, the area on the substrate occupied by the active chip component is approximately equal to the area of the active chip component.

Abstract: An electronic assembly (10) comprises one or more electronic components (18) having solder terminations (20), and a printed circuit substrate (12) having printed circuit traces (14, 16), wherein at least one of the solder terminations of the one or more electronic components (18) and the printed circuit traces (14, 16) of the printed circuit substrate (12) has a secondary finish produced by application of an electrolessly deposited nickel film (26) containing phosphorus which is further plated with gold (28). An indium-tin-lead solder paste (22) is utilized in a soldering process to attached the one or more electronics components (18) to the printed circuit traces (14,16) on the printed circuit board (12), such that the indium-tin-lead solder (22) provides improved solder joint integrity with the secondary finish. The electronic components (18) include semiconductor devices such as ball grid arrays (1000) and flip-chip integrated circuits (1010).

Abstract: A display module (207) is used that integrates circuit components (402-422) thereto. The display module (207) includes a displayable element (101), and a first conductive runner (206) located on a backside of the display module (207) that couples to the displayable element (101). Additionally, display module (207) includes at least one layer of substrate material (208, 210) covering the backside of the display module (207) with a portion of the first conductive runner (206) exposed, and a first conductive coupling element (212, 302) coupled to the portion of the first conductive runner (206).

Abstract: A novel process for plating a substrate without solder mask wherein the substrate is coated with a polymer catalyst to assist adhesion of conductive metal to the substrate. Next, a first plating mask photopolymer, or plating resist, is coated over the polymer catalyst, a circuit pattern is imaged onto the first plating mask and the first plating mask is developed to reveal windows, or circuit traces, in the first plating mask corresponding to the circuit pattern to be embodied on the substrate. Thereafter, a first conductive material such as copper is plated into the windows, and, thereafter, a second conductive material such as nickel may be plated into the windows on top of the first conductive material. Then, the first plating mask is removed from the substrate, leaving behind the conductive material in the form of the desired circuit pattern.

Abstract: A method of producing multi-layered chip carriers by coating the surface of a base layer with a photosensitive dielectric material which forms a dielectric layer; curing at least a portion of the dielectric layer by exposure to radiation; depositing a catalyst on the cured portion of the dielectric layer to form a sensitized dielectric layer; applying a photoresist layer upon the sensitized dielectric layer; curing at least a portion of the photoresist layer; developing the cured photoresist layer by removing uncured portions, thereby exposing corresponding portions of the underlying sensitized dielectric layer; forming conductors on the exposed dielectric layer; stripping the cured photoresist layer: coating a layer of photosensitive dielectric material upon the cured dielectric layer; and repeating the steps to produce successive layers which form a multi-layer chip carrier having a plurality of conductor layers separated by layers of insulating dielectric material.

Abstract: A method of interconnecting circuit modules (30) to mother boards (50) each having a plurality of mating solder pads (32, 52) is available. The solder pads (32, 52) have respective pairs of arms (40, 42) and (54, 56) with a venting channel (36, 58) formed between each pair of arms to vent solder medium when the solder pads are reflowed to interconnect the circuit modules and mother boards.

Abstract: A wire bond pad arrangement (104) has an improved pad density for providing a plurality of wire bond terminations for interconnection with corresponding terminations (604) of an IC chip (302. The wire bond pad arrangement (104) includes a substrate (102) and a plurality of pads (912) disposed on the substrate (102) adjacent to one another to form a row of pads (912). Each of the pads (912) is formed in a trapezoidal shape having short and long sides parallel to one another and substantially perpendicular to a line from a central point of the pad (912) to a central point of the corresponding termination (604) of the IC chip (302). The long sides of adjacent pads (912) are positioned alternately towards and away from the corresponding terminations (604) of the IC chip 302).

Abstract: A method and apparatus for use in forming pre-positioned solder bumps (104) on a pad arrangement (100) of a substrate (101) include placing a predetermined pattern (306) of solder preforms (304) in contact with a meltable adhesive fluxing agent (302) on a carrier tape (402), and then heating the fluxing agent (302) to melt it. Next, the fluxing agent (302) is cooled to resolidify it, thereby securing the solder preforms (304) to the carrier tape (402). The carrier tape (402) is then aligned over the pad arrangement (100) and the solder preforms (304) are transferred to the pad arrangement (100) by heating the solder preforms (304) to form the solder bumps (104) in the predetermined pattern (306).