Patents by Inventor Frank K. Baker, Jr.
Frank K. Baker, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10642602Abstract: A software update architecture, system, apparatus, and methodology are provided for performing block-based swapping of OTA software stored as a plurality of compressed blocks in a first, smaller NVM with the system software stored as a plurality of decompressed blocks in a second, larger NVM by using a first decompressor circuit and first scratch memory to sequentially decompress each compressed code block of OTA software for storage in decompressed form as updated system software in the second, larger NVM while using a first compressor circuit and second scratch memory to sequentially compress each decompressed code block of system software for storage in compressed form as backup system software in the first, smaller NVM.Type: GrantFiled: December 12, 2017Date of Patent: May 5, 2020Assignee: NXP USA, Inc.Inventors: Anirban Roy, Anis M. Jarrar, Frank K. Baker, Jr.
-
Publication number: 20190179629Abstract: A software update architecture, system, apparatus, and methodology are provided for performing block-based swapping of OTA software stored as a plurality of compressed blocks in a first, smaller NVM with the system software stored as a plurality of decompressed blocks in a second, larger NVM by using a first decompressor circuit and first scratch memory to sequentially decompress each compressed code block of OTA software for storage in decompressed form as updated system software in the second, larger NVM while using a first compressor circuit and second scratch memory to sequentially compress each decompressed code block of system software for storage in compressed form as backup system software in the first, smaller NVM.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Applicant: NXP USA, Inc.Inventors: Anirban Roy, Anis M. Jarrar, Frank K. Baker, JR.
-
Patent number: 9792981Abstract: A non-volatile memory includes a first bit cell having a programmable resistive element coupled to a write bit line wherein the programmable resistive element is programmable to one of two resistive states, a resistive element coupled to the programmable resistive element at a circuit node, and a first transistor configured to operate in saturation during a read operation. The first transistor has a control electrode coupled to the circuit node and a first current electrode coupled to a read bit line.Type: GrantFiled: September 29, 2015Date of Patent: October 17, 2017Assignee: NXP USA, Inc.Inventors: Perry H. Pelley, Frank K. Baker, Jr.
-
Patent number: 9779807Abstract: A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail.Type: GrantFiled: July 31, 2014Date of Patent: October 3, 2017Assignee: NXP USA, Inc.Inventors: Perry H. Pelley, Frank K. Baker, Jr.
-
Patent number: 9734905Abstract: A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted.Type: GrantFiled: May 27, 2016Date of Patent: August 15, 2017Assignee: NXP USA, Inc.Inventor: Frank K. Baker, Jr.
-
Patent number: 9666276Abstract: A memory cell includes a first storage node and a second storage node that is complementary to the first storage node. A first bidirectional resistive memory element (BRME) includes a first terminal, a second BRME includes a first terminal. A first access transistor couples the first storage node to a first bit line. A second access transistor couples the second storage node to a second bit line. A third transistor couples the first terminal of the first BRME to the second bit line. A fourth transistor couples the first terminal of the second BRME to the first bit line.Type: GrantFiled: April 30, 2014Date of Patent: May 30, 2017Assignee: NXP USA, Inc.Inventor: Frank K. Baker, Jr.
-
Publication number: 20170092354Abstract: A non-volatile memory includes a first bit cell having a programmable resistive element coupled to a write bit line wherein the programmable resistive element is programmable to one of two resistive states, a resistive element coupled to the programmable resistive element at a circuit node, and a first transistor configured to operate in saturation during a read operation. The first transistor has a control electrode coupled to the circuit node and a first current electrode coupled to a read bit line.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Inventors: PERRY H. PELLEY, FRANK K. BAKER JR.
-
Patent number: 9530501Abstract: A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block includes a shared port communicatively coupled to a block, the block comprising a plurality of memory cells, wherein the shared port is operable to sense a voltage level at each of the plurality of memory cells. The plurality of decoded address signals are communicatively coupled to the block. Each of the plurality of decoded address signals is operable to enable a corresponding one of the plurality of memory cells. The read signal is communicatively coupled to the shared port. The read signal is operable to enable a read operation associated with the block. The read word line signal is communicatively coupled to the shared port block. The read word line signal is operable to enable the read operation.Type: GrantFiled: December 31, 2014Date of Patent: December 27, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Perry H. Pelley, Frank K. Baker, Jr., Ravindraraj Ramaraju
-
Patent number: 9520173Abstract: A memory device includes a first memory cell having a first transistor, a second transistor, and a resistive storage element. During a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element. During a write operation, current is conducted through the first and second transistors.Type: GrantFiled: February 29, 2016Date of Patent: December 13, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Frank K. Baker, Jr., Michael A. Sadd, Anirban Roy, Bruce L. Morton
-
Publication number: 20160276029Abstract: A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted.Type: ApplicationFiled: May 27, 2016Publication date: September 22, 2016Inventor: Frank K. Baker Jr.
-
Patent number: 9401207Abstract: A memory device includes a first select transistor having a first current electrode coupled to a first bit line, a control electrode and a second current electrode. A second select transistor has a first current electrode coupled to a second bit line, a control electrode and a second current electrode. A first bi-directional resistive element has a cathode coupled to the second current electrode of the first select transistor and an anode coupled to an internal node. A second bi-directional resistive element has a cathode coupled to the internal node and an anode coupled to the second current electrode of the second select transistor. A third transistor has a first current electrode coupled to a third bit line, a second current electrode coupled to the internal node, and a control electrode coupled to a word line.Type: GrantFiled: December 12, 2014Date of Patent: July 26, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Anirban Roy, Frank K. Baker, Jr.
-
Publication number: 20160188457Abstract: A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block includes a shared port communicatively coupled to a block, the block comprising a plurality of memory cells, wherein the shared port is operable to sense a voltage level at each of the plurality of memory cells. The plurality of decoded address signals are communicatively coupled to the block. Each of the plurality of decoded address signals is operable to enable a corresponding one of the plurality of memory cells. The read signal is communicatively coupled to the shared port. The read signal is operable to enable a read operation associated with the block. The read word line signal is communicatively coupled to the shared port block. The read word line signal is operable to enable the read operation.Type: ApplicationFiled: December 31, 2014Publication date: June 30, 2016Inventors: PERRY H. PELLEY, FRANK K. BAKER, Jr., RAVINDRARAJ RAMARAJU
-
Patent number: 9378812Abstract: A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted.Type: GrantFiled: May 28, 2014Date of Patent: June 28, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Frank K. Baker, Jr.
-
Publication number: 20160172035Abstract: A memory device includes a first select transistor having a first current electrode coupled to a first bit line, a control electrode and a second current electrode. A second select transistor has a first current electrode coupled to a second bit line, a control electrode and a second current electrode. A first bi-directional resistive element has a cathode coupled to the second current electrode of the first select transistor and an anode coupled to an internal node. A second bi-directional resistive element has a cathode coupled to the internal node and an anode coupled to the second current electrode of the second select transistor. A third transistor has a first current electrode coupled to a third bit line, a second current electrode coupled to the internal node, and a control electrode coupled to a word line.Type: ApplicationFiled: December 12, 2014Publication date: June 16, 2016Inventors: ANIRBAN ROY, FRANK K. BAKER, JR.
-
Patent number: 9318158Abstract: A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.Type: GrantFiled: May 27, 2014Date of Patent: April 19, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Frank K. Baker, Jr., Perry H. Pelley, Ravindraraj Ramaraju
-
Patent number: 9281042Abstract: A memory cell includes a bi-directional resistive memory element, a first transistor, and a capacitive element. The bi-directional resistive memory element has a first terminal directly connected to a first power rail and a second terminal coupled to an internal node. The first transistor has a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to one of the first power rail, a second power rail, or a read wordline. The capacitive element includes a first terminal coupled to the internal node and a second terminal coupled to the read wordline.Type: GrantFiled: December 17, 2014Date of Patent: March 8, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Perry H. Pelley, Frank K. Baker, Jr., Ravindraraj Ramaraju
-
Patent number: 9276008Abstract: A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.Type: GrantFiled: March 18, 2015Date of Patent: March 1, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Jon D. Cheek, Frank K. Baker, Jr.
-
Publication number: 20160035415Abstract: A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail.Type: ApplicationFiled: July 31, 2014Publication date: February 4, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: PERRY H. PELLEY, Frank K. Baker, JR.
-
Publication number: 20150348595Abstract: A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.Type: ApplicationFiled: May 27, 2014Publication date: December 3, 2015Inventors: Frank K. Baker, JR., Perry H. Pelley, Ravindraraj Ramaraju
-
Publication number: 20150318024Abstract: A memory cell includes a first storage node and a second storage node that is complementary to the first storage node. A first bidirectional resistive memory element (BRME) includes a first terminal, a second BRME includes a first terminal. A first access transistor couples the first storage node to a first bit line. A second access transistor couples the second storage node to a second bit line. A third transistor couples the first terminal of the first BRME to the second bit line. A fourth transistor couples the first terminal of the second BRME to the first bit line.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Inventor: FRANK K. BAKER, JR.