Abstract: A self-test device for memory arrangements, decoders or the like for use during on-line operation, the word lines and/or the column lines of a memory matrix being connected to a check matrix. An error detector which generates an error signal if more than one line is activated simultaneously is connected to the check matrix. Since multiple word lines or column lines are activated in the decoder for most errors which occur, a simple self-test can be performed during on-line operation by this check matrix which can be implemented in a relatively simple and cost-effective manner.

Abstract: A self-testing method for irregular CMOS switching structures with high defect detection is described which combines self testing with linear feedback shift registers and the principle of sensing the static current consumption and partitioning the circuit to be tested. This combination of the two test principles advantageously results in high detection of parametric faults, such as delay faults, high-resistance bridge faults, and functional faults, such as stuck-at, stuck-open and low-resistance bridge faults, in conjunction with a relatively low additional hardware expense.