Abstract: A data processing device (100) characterizes behavior properties of equipment under observation (105). The device (100) has a plurality of processing units that are adapted to process input values (a) to output values (e) according to numerical transfer functions. The functions implement an input-to-output mapping specified by a configuration (C) that is obtained by pre-processing historic data (114) from a plurality of master equipment (104). The configuration is related to the behavior properties of the equipment (105) so that some of the output values (e) represent the behavior properties of the equipment (105) under observation.

Abstract: A data processing device (100) characterizes behavior properties of equipment under observation (105). The device (100) has a plurality of processing units that are adapted to process input values (a) to output values (e) according to numerical transfer functions. The functions implement an input-to-output mapping specified by a configuration (C) that is obtained by pre-processing historic data (114) from a plurality of master equipment (104). The configuration is related to the behavior properties of the equipment (105) so that some of the output values (e) represent the behavior properties of the equipment (105) under observation.

Abstract: A data processing device (100) characterizes behavior properties of equipment under observation (105). The device (100) has a plurality of processing units that are adapted to process input values (a) to output values (e) according to numerical transfer functions. The functions implement an input-to-output mapping specified by a configuration (C) that is obtained by pre-processing historic data (114) from a plurality of master equipment (104). The configuration is related to the behavior properties of the equipment (105) so that some of the output values (e) represent the behavior properties of the equipment (105) under observation.

Abstract: A data processing device (100) characterizes behavior properties of equipment under observation (105). The device (100) has a plurality of processing units that are adapted to process input values (a) to output values (e) according to numerical transfer functions. The functions implement an input-to-output mapping specified by a configuration (C) that is obtained by pre-processing historic data (114) from a plurality of master equipment (104). The configuration is related to the behavior properties of the equipment (105) so that some of the output values (e) represent the behavior properties of the equipment (105) under observation.

Abstract: A data processing device (100) characterizes behavior properties of equipment under observation (105). The device (100) has a plurality of processing units that are adapted to process input values (a) to output values (e) according to numerical transfer functions. The functions implement an input-to-output mapping specified by a configuration (C) that is obtained by pre-processing historic data (114) from a plurality of master equipment (104). The configuration is related to the behavior properties of the equipment (105) so that some of the output values (e) represent the behavior properties of the equipment (105) under observation.

Abstract: A data processing device (100) characterizes behavior properties of equipment under observation (105). The device (100) has a plurality of processing units that are adapted to process input values (a) to output values (e) according to numerical transfer functions. The functions implement an input-to-output mapping specified by a configuration (C) that is obtained by pre-processing historic data (114) from a plurality of master equipment (104). The configuration is related to the behavior properties of the equipment (105) so that some of the output values (e) represent the behavior properties of the equipment (105) under observation.

Abstract: The method includes defining from all the check nodes at least one group of check nodes mutually connected through at least one second variable node defining an internal second variable node. The method includes performing for each group the joint updating of all the check nodes of the group via a Maximum-A-Posteriori (MAP) type process, and the updating of all the first variable nodes and all the second variable nodes connected to the group except the at least one internal second variable node. The method may include iteratively repeating the updates.

Abstract: This is a method for controlling the decoding of a LDPC encoded codeword composed of several digital data, said LDPC code being represented by a bipartite graph between check nodes (CN1) and variable nodes (VNi). Said method comprises updating messages exchanged iteratively between variable nodes (VN1) and check nodes (CN1). Said method comprises, at each iteration, calculating for each variable node a first sum (?n) of all the incident messages (?i) received by said variable node and the corresponding digital data (?ch) and calculating a second sum (VNRnew) of all the absolute values of the first sums (?n), and stopping the decoding process if the second sum (VNRnew) is unchanged or decreases within two successive iterations and if a predetermined threshold condition is satisfied.

Abstract: The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.

Abstract: The method is for decoding an LDPC encoded codeword, the LDPC code being represented by a bipartite graph between check nodes and variable nodes including first variable nodes and second variable nodes connected to the check nodes by a zigzag connectivity. The method includes updating messages exchanged iteratively between variable nodes and check nodes including a first variable processing phase during which all the messages from the first variable nodes to the check nodes are updated and a check nodes processing phase during which all the messages from the check nodes to the first variable nodes are updated. The check nodes processing phase further includes updating all the messages from the second variable nodes to the check nodes, and directly passing an updated message processed by a check node to the next check node through the zigzag connectivity.

Abstract: This is a method for controlling the decoding of a LDPC encoded codeword composed of several digital data, said LDPC code being represented by a bipartite graph between check nodes (CN1) and variable nodes (VNi). Said method comprises updating messages exchanged iteratively between variable nodes (VN1) and check nodes (CN1). Said method comprises, at each iteration, calculating for each variable node a first sum (?n)=of all the incident messages (?i) received by said variable node and the corresponding digital data (?ch) and calculating a second sum (VNRnew) of all the absolute values of the first sums (?n), and stopping the decoding process if the second sum (VNRnew) is unchanged or decreases within two successive iterations and if a predetermined threshold condition is satisfied.

Abstract: The method is for decoding an LDPC encoded codeword, the LDPC code being represented by a bipartite graph between check nodes and variable nodes including first variable nodes and second variable nodes connected to the check nodes by a zigzag connectivity. The method includes updating messages exchanged iteratively between variable nodes and check nodes including a first variable processing phase during which all the messages from the first variable nodes to the check nodes are updated and a check nodes processing phase during which all the messages from the check nodes to the first variable nodes are updated. The check nodes processing phase further includes updating all the messages from the second variable nodes to the check nodes, and directly passing an updated message processed by a check node to the next check node through the zigzag connectivity.

Abstract: The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.