Abstract: The present invention relates to a method for producing a sport beverage, comprising the steps of providing malt and/or unmalted grains, providing mashing liquor produced from spent grains, processing the malt and the mashing liquor to obtain a wort, fermenting the wort by using a yeast and optionally, blending with flavour(s) and/or vitamin(s); and/or adding of sugar(s). The present invention further relates to a sport beverage obtained by said method, wherein said sport beverage is non-alcoholic or has an alcohol content of less than about 1.2 vol-%, preferably less than about 0.5 vol-%. The present invention also relates to the use of the sport beverage before and/or after physical activities.

Abstract: A decision feedback structure for recovering a bit stream out of received signals is disclosed, wherein the sampling instant may be tuned in dependence of the sequence or pattern of the preceding bits so as to follow the bit sequence dependent instant of the maximum eye opening. The decision-feedback equalizer structure includes decision means for making a bit value decision at a sampling instant, a feedback path to feed back bit values to said decision means and means for adapting the sampling instant for a bit value decision made by said decision means with respect to the sampling phase depending on the bit values of preceding bits, in particular depending on the bit value of the previous bit.

Abstract: A method and a device for monitoring a rotational speed of a first charger for an internal combustion engine, especially an exhaust gas turbocharger, are provided. A first exhaust value representing an exhaust gas composition of the internal combustion engine in a first exhaust section is defined, and a first speed value representing the rotational speed of the first charger is determined according to the defined first exhaust value. The first exhaust value is regulated to a predefined first reference value using a first correcting variable which is ascertained as required for regulation. The first rotational speed value is determined depending on the first correcting variable.

Abstract: A method for correcting the phase of a clock in a data receiver which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) or a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single signal values (1,0) of different signal levels.

Abstract: A circuit for generating a digital data signal from an analog input data signal is disclosed. The circuit comprises a master-slave flip-flop with a clock input for receiving the analog input data signal, an amplitude detecting circuit for detecting the amplitude of the analog input data signal and generating an amplitude detection signal in response thereto, and a phase shifting circuit responsive to the amplitude detection signal for supplying a phase shifted signal to the clock input of the master-slave flip-flop. The circuit may further include a clock recovery circuit for generating a recovered clock signal from a clock signal contained in the analog input data signal. The recovered clock signal may be supplied to the amplitude detecting circuit, or a feedback loop may supply the phase shifted clock signal to the amplitude detecting circuit.

Abstract: A decision feedback structure for recovering a bit stream out of received signals is disclosed, wherein the sampling instant may be tuned in dependence of the sequence or pattern of the preceding bits so as to follow the bit sequence dependent instant of the maximum eye opening. The decision-feedback equalizer structure includes decision means for making a bit value decision at a sampling instant, a feedback path to feed back bit values to said decision means and means for adapting the sampling instant for a bit value decision made by said decision means with respect to the sampling phase depending on the bit values of preceding bits, in particular depending on the bit value of the previous bit.

Abstract: A method for correcting the phase of a clock in a data receiver which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) or a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single signal values (1,0) of different signal levels.

Abstract: The invention relates to an actuator (5) which is impinged by a force in one end position and is displaced into the other end position by an adjusting device (54) that is controlled using a pulse duration modulated signal. According to said invention, if a quasi-stationary condition is identified, in which despite repeated control intervention the actual position of the actuator lies outside a targeted range around the desired position, the retaining pulse duty factor which is used by the adjusting device (54) to maintain the actuator (5) in one position is modified based on the distance from the desired position. If a drift is identified, the drift behaviour is determined and the retaining pulse duty factor is modified according to said drift behaviour.

Abstract: A circuit for generating a digital data signal from an analog input data signal is disclosed. The circuit comprises a master-slave flip-flop with a clock input for receiving the analog input data signal, an amplitude detecting circuit for detecting the amplitude of the analog input data signal and generating an amplitude detection signal in response thereto, and a phase shifting circuit responsive to the amplitude detection signal for supplying a phase shifted signal to the clock input of the master-slave flip-flop. The circuit may further include a clock recovery circuit for generating a recovered clock signal from a clock signal contained in the analog input data signal. The recovered clock signal may be supplied to the amplitude detecting circuit, or a feedback loop may supply the phase shifted clock signal to the amplitude detecting circuit.