Abstract: A data processing system (10) uses a microprocessor host (12) coupled to a decoding system (14). A hardware filter arithmetic unit block (32) retrieves decoded information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). An address circuit forms several addresses from a single value to accesses multiple sources of data and coefficients simultaneously for use by the hardware filter arithmetic unit.

Abstract: A video data processing system (10) has a first substrate (12) and a second substrate (14). A system decoder (16), input buffer (18) and parser (20) are formed on first substrate (12). The parser (20) retrieves video data information from an input data stream and feeds coefficients through a dequantization unit (22) and a transformation unit (24). In addition, motion vector information is output from the parser (20). The second substrate (14) comprises a plurality of picture frame buffers 38, 40 and 44. The frame buffers 38, 40 and 44 are used to store decoded video information. Motion compensation modules 26a and 26b are used to perform predicted calculations on the information received from the video data stream as well as other images that have already been decoded. A raster scan output buffer (46) is used to output the decoded video information.

Abstract: A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

Abstract: A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

Abstract: A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

Abstract: A video data processing system (10) has a first substrate (12) and a second substrate (14). A system decoder (16), input buffer (18) and parser (20) are formed on first substrate (12). The parser (20) retrieves video data information from an input data stream and feeds coefficients through a dequantization unit (22) and a transformation unit (24). In addition, motion vector information is output from the parser (20). The second substrate (14) comprises a plurality of picture frame buffers 38, 40 and 44. The frame buffers 38, 40 and 44 are used to store decoded video information. Motion compensation modules 26a and 26b are used to perform predicted calculations on the information received from the video data stream as well as other images that have already been decoded. A raster scan output buffer (46) is used to output the decoded video information.

Abstract: An audio data processing system (10) is described which comprises a control processor (12) coupled to an execution controller (22) through a bus (21). The control processor (12) serves as a master processor to control the operation of the execution controller (22) which in turn controls the operation of a multiplier accumulator (28). An ancillary data handler (20) is provided to retrieve ancillary data from an input FIFO buffer (18). Audio data is retrieved from the input FIFO buffer (18) by the control processor (12) and processed audio data is output through an output block (30).

Abstract: A data processing system (10) is described which comprises an integrated decoder circuit (12) comprising an input buffer (14) and an error signal generator circuit ( 18 ) . The error signal generator circuit ( 18 ) generates a pulse width modulated error signal output to a clock processing circuit (20). The clock processing circuit (20) may comprise a low pass filter (24) and a variable oscillator (26). The clock processing circuit (20) supplies a clock signal to a digital-to-analog converter (16). The digital-to-analog converter (16) uses the clock signal to correctly track the bit rate for the encoded bit stream received by decoder system (12).