Patents by Inventor Frank L. Pompeo

Frank L. Pompeo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190281702
    Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 12, 2019
    Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
  • Publication number: 20190259632
    Abstract: A fixture to facilitate fabrication of a heat sink includes a base plate to support a lower section of the heat sink, and multiple registration pins extending from the base plate. A platen is provided over a heat transfer element (HTE) of the heat sink, with the platen including slip fit regions to slip fit around respective registration pins, and with the lower section and HTE disposed between the base plate and the platen, and forming a fixture stack segment aligned with an active region of the cold plate. A load plate is provided which includes slip fit regions configured to slip fit around corresponding registration pins with the load plate disposed over the fixture stack segment. The load plate includes a single load pin centrally disposed to apply a load to the fixture stack segment and facilitate bonding the lower section and HTE together.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 22, 2019
    Inventors: Phillip D. ISAACS, Christopher M. MARROQUIN, Daren SIMMONS, Frank L. POMPEO, Jason R. EAGLE, Mark K. HOFFMEYER, Michael J. ELLSWORTH, JR., Prabjit SINGH, Steve OSTRANDER
  • Patent number: 10368441
    Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
  • Publication number: 20180213645
    Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.
    Type: Application
    Filed: March 22, 2018
    Publication date: July 26, 2018
    Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
  • Patent number: 9974179
    Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: May 15, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
  • Publication number: 20170196089
    Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.
    Type: Application
    Filed: March 22, 2017
    Publication date: July 6, 2017
    Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
  • Patent number: 9627784
    Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
  • Patent number: 8492199
    Abstract: The present invention provides chip containing electronic devices such as Multichip Ceramic Modules (MCM's) containing a plurality of chips on a substrate which chips are underfilled with a reworkable composition which allows one or more chips to be removed from the device and replaced. The reworkable compositions contain a base resin which is not cross-linkable and which forms a matrix with a linear curable component or preferably a combination of linear curable components which curable components are cross-linkable and when cured form a cross-linked domain in the base resin matrix. A suitable cross-linking catalyst such as Pt is used and optionally a filler preferably silane surface treated silica. The preferred base resin is linear polydimethylsiloxane and the preferred curable components are vinyl terminated linear poly dimethyl siloxane and hydrogen terminated linear poly dimethyl siloxane.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey T. Coffin, Steven P. Ostrander, Frank L. Pompeo, Jiali Wu
  • Publication number: 20120021567
    Abstract: The present invention provides chip containing electronic devices such as Multichip Ceramic Modules (MCM's) containing a plurality of chips on a substrate which chips are underfilled with a reworkable composition which allows one or more chips to be removed from the device and replaced. The reworkable compositions contain a base resin which is not cross-linkable and which forms a matrix with a linear curable component or preferably a combination of linear curable components which curable components are cross-linkable and when cured form a cross-linked domain in the base resin matrix. A suitable cross-linking catalyst such as Pt is used and optionally a filler preferably silane surface treated silica. The preferred base resin is linear polydimethylsiloxane and the preferred curable components are vinyl terminated linear poly dimethyl siloxane and hydrogen terminated linear poly dimethyl siloxane.
    Type: Application
    Filed: October 4, 2011
    Publication date: January 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey T. Coffin, Steven P. Ostrander, Frank L. Pompeo, Jiali Wu
  • Patent number: 7900809
    Abstract: A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Glenn G. Daves, David L. Edwards, Mukta G. Farooq, Frank L. Pompeo
  • Patent number: 7882623
    Abstract: Disclosed is an apparatus for separating interconnects between, for example, a card and a substrate. The apparatus includes one or more rotationally biased (e.g., spring-loaded, etc.) partial-circle structures (e.g., blades, squeegee, plow, etc.) and one or more temperature-sensitive releases connected to the partial-circle structures. The partial-circle structures are positioned to rotate and separate the interconnects when released by the temperature-sensitive releases. The invention can also include solder reservoirs positioned to receive solder from the interconnects separated by the partial-circle structures.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ray A. Jackson, David C. Linnell, Frank L. Pompeo
  • Patent number: 7806341
    Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Benjamin V. Fasano, Jason L. Frankel, Harvey C. Hamel, Suresh D. Kadakia, David C. Long, Frank L. Pompeo, Sudipta K. Ray
  • Publication number: 20090145973
    Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.
    Type: Application
    Filed: January 5, 2009
    Publication date: June 11, 2009
    Applicant: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Benjamin V. Fasano, Jason L. Frankel, Harvey C. Hamel, Suresh D. Kadakia, David C. Long, Frank L. Pompeo, Sudipta K. Ray
  • Patent number: 7544527
    Abstract: An optoelectronic assembly for an electronic system includes a thermally conductive, metallized transparent substrate having a first surface and an opposite second surface. A support chip set is bonded to the transparent substrate. A first substrate is in communication with the transparent substrate via the second surface and support chip set therebetween. A second substrate is in communication with the second surface of the first substrate and is configured for mounting at least one of data processing, data switching and data storage chips. An optoelectronic transducer is in signal communication with the support chip set, and an optical signaling medium having one end with an optical fiber array aligned with the transducer is substantially normal to the first surface of the transparent substrate. The support chip set and the transducer share a common thermal path for cooling.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: June 9, 2009
    Assignee: International Business Machines Corporation
    Inventors: Alan F. Benner, How Tzu Lin, Frank L. Pompeo, Subhash L. Shinde
  • Patent number: 7472836
    Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Benjamin V. Fasano, Jason L. Frankel, Harvey C. Hamel, Suresh D. Kadakia, David C. Long, Frank L. Pompeo, Sudipta K. Ray
  • Patent number: 7452215
    Abstract: Disclosed is an apparatus for separating interconnects between, for example, a card and a substrate. The apparatus includes one or more rotationally biased (e.g., spring-loaded, etc.) partial-circle structures (e.g., blades, squeegee, plow, etc.) and one or more temperature-sensitive releases connected to the partial-circle structures. The partial-circle structures are positioned to rotate and separate the interconnects when released by the temperature-sensitive releases. The invention can also include solder reservoirs positioned to receive solder from the interconnects separated by the partial-circle structures.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ray A. Jackson, David C. Linnell, Frank L. Pompeo
  • Publication number: 20080271312
    Abstract: Disclosed is an apparatus for separating interconnects between, for example, a card and a substrate. The apparatus includes one or more rotationally biased (e.g., spring-loaded, etc.) partial-circle structures (e.g., blades, squeegee, plow, etc.) and one or more temperature-sensitive releases connected to the partial-circle structures. The partial-circle structures are positioned to rotate and separate the interconnects when released by the temperature-sensitive releases. The invention can also include solder reservoirs positioned to receive solder from the interconnects separated by the partial-circle structures.
    Type: Application
    Filed: July 18, 2008
    Publication date: November 6, 2008
    Applicant: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ray A. Jackson, David C. Linnell, Frank L. Pompeo
  • Patent number: 7445141
    Abstract: A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Glenn G. Daves, David L. Edwards, Mukta G. Farooq, Frank L. Pompeo
  • Publication number: 20080261350
    Abstract: A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.
    Type: Application
    Filed: June 26, 2008
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Glenn G. Daves, David L. Edwards, Mukta G. Farooq, Frank L. Pompeo
  • Publication number: 20070290378
    Abstract: The present invention provides chip containing electronic devices such as Multichip Ceramic Modules (MCM's) containing a plurality of chips on a substrate which chips are underfilled with a reworkable composition which allows one or more chips to be removed from the device and replaced. The reworkable compositions contain a base resin which is not cross-linkable and which forms a matrix with a linear curable component or preferably a combination of linear curable components which curable components are cross-linkable and when cured form a cross-linked domain in the base resin matrix. A suitable cross-linking catalyst such as Pt is used and optionally a filler preferably silane surface treated silica. The preferred base resin is linear polydimethylsiloxane and the preferred curable components are vinyl terminated linear poly dimethyl siloxane and hydrogen terminated linear poly dimethyl siloxane.
    Type: Application
    Filed: June 20, 2006
    Publication date: December 20, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey T. Coffin, Steven P. Ostrander, Frank L. Pompeo, Jiali Wu