Abstract: A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8×8 sub-regions which encompasses the entire scene area. There is then a group of four 4×4 sets of sub-regions, then a group of sixteen 2×2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.

Abstract: A tile-based graphics processing pipeline includes a back-facing determination and culling unit that is operable to cull back-facing triangles before the tiling stage. The back-facing determination and culling unit include a triangle size estimator that estimates the size of a triangle being considered. If the size of the triangle is less than a selected size, then the area of the triangle is calculated using fixed point arithmetic and the result of that area calculation is used by a back-face culling unit to determine whether to cull the triangle or not. On the other hand, if the size estimator determines that the primitive is greater than the selected size, then the triangle bypasses the fixed point area calculation and back-face culling unit and is instead passed directly to the tiler.

Abstract: When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.

Abstract: When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.

Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.

Abstract: A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8×8 sub-regions which encompasses the entire scene area. There is then a group of four 4×4 sets of sub-regions, then a group of sixteen 2×2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.

Abstract: A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8×8 sub-regions which encompasses the entire scene area. There is then a group of four 4×4 sets of sub-regions, then a group of sixteen 2×2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.

Abstract: A graphics processor includes a graphics object list building unit that determines the location of each draw call in a scene to be rendered and generates a list of draw calls for each sub-region (tile) that the scene to be rendered is divided into. The draw call lists are stored in a memory. A graphics object selection unit of a renderer of the graphics processor then determines which draw call is to be rendered next by considering the draw call list stored in the memory for the sub-region (tile) of the scene that is currently being rendered.

Abstract: A graphics processing pipeline (20) comprises first vertex shading circuitry (21) that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline. Tiling circuitry (22) then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. A second vertex shading circuitry (23) then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further.

Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.

Abstract: A tile-based graphics processing pipeline includes a back-facing determination and culling unit that is operable to cull back-facing triangles before the tiling stage. The back-facing determination and culling unit include a triangle size estimator that estimates the size of a triangle being considered. If the size of the triangle is less than a selected size, then the area of the triangle is calculated using fixed point arithmetic and the result of that area calculation is used by a back-face culling unit to determine whether to cull the triangle or not. On the other hand, if the size estimator determines that the primitive is greater than the selected size, then the triangle bypasses the fixed point area calculation and back-face culling unit and is instead passed directly to the tiler.

Abstract: A graphics processing pipeline (20) comprises first vertex shading circuitry (21) that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline. Tiling circuitry (22) then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. A second vertex shading circuitry (23) then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further.

Abstract: A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8×8 sub-regions which encompasses the entire scene area. There is then a group of four 4×4 sets of sub-regions, then a group of sixteen 2×2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.

Abstract: In a tile-based graphics processor, primitive lists (bins) are prepared for 2×2 blocks of tiles 40. The processor also determines and stores for each primitive in a bin, distribution information indicating the distribution of the primitive within the set of tiles that the bin corresponds to. Thus a primitive 42 that is found by its bounding box 43 to reside in two of the four tiles that make up the set of 2×2 tiles 40 is also associated with a tile coverage bitmap of the form “0101” to indicate that it lies in tiles “1” and “3” of the 2×2 group of tiles 40. The graphics processor uses the coverage bitmap (information) to determine whether a primitive should be processed for the tile currently being processed.

Abstract: A distribution medium (20) for providing an application to a host system (4) includes an interface element (21) for interfacing with the host (4), a memory or storage module (22) that stores application code representing the application and a hardware element (23). The hardware element (23) directly accesses application content stored in the memory (22), processes that application content to transform it to another form, and then provides the transformed content to the host system (4).

Abstract: In a tile-based graphics processor, primitive lists (bins) are prepared for 2×2 blocks of tiles 40. The processor also determines and stores for each primitive in a bin, distribution information indicating the distribution of the primitive within the set of tiles that the bin corresponds to. Thus a primitive 42 that is found by its bounding box 43 to reside in two of the four tiles that make up the set of 2×2 tiles 40 is also associated with a tile coverage bitmap of the form “0101” to indicate that it lies in tiles “1” and “3” of the 2×2 group of tiles 40. The graphics processor uses the coverage bitmap (information) to determine whether a primitive should be processed for the tile currently being processed.

Abstract: A distribution medium (20) for providing an application to a host system (4) includes an interface element (21) for interfacing with the host (4), a memory or storage module (22) that stores application code representing the application and a hardware element (23). The hardware element (23) directly accesses application content stored in the memory (22), processes that application content to transform it to another form, and then provides the transformed content to the host system (4).

Abstract: A graphics processor 20 includes a graphics object list building unit 28 that determines the location of each draw call in a scene to be rendered and generates a list of draw calls for each sub-region (tile) that the scene to be rendered is divided into. The draw call lists are stored in a memory 23. A graphics object selection unit 29 of a renderer 22 of the graphics processor 20 then determines which draw call is to be rendered next by considering the draw call list 26 stored in the memory 23 for the sub-region (tile) of the scene that is currently being rendered.

Abstract: A scene 50 to be rendered is divided into plural individual sub-regions or tiles 51. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set 54 of 8×8 sub-regions which encompasses the entire scene area 50. There is then a group of four 4×4 sets of sub-regions 53, then a group of sixteen 2×2 sets of sub-regions 52, and finally a layer comprising the 64 single sub-regions 51. A primitive list building unit takes each primitive 80 in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions 51 and the locations of the sets of sub-regions 52, 53 and 54, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.

Abstract: Methods and apparatus for stepping-over and stepping-out of functions encountered during program execution on a target processor during debug operations are implemented within a combination of an emulator and a debug module. By having communication and storage devices available on-chip in the debug module, stepping and address compare details are conducted local to the processor at hardware speeds. The methods correctly determine necessary algorithmic steps to accommodate recursive and nested function calls without intervention by a combination of a host debug platform and a debug software application. This avoids the amount of time that would otherwise be necessary to cycle communications to the debug host level to accomplish the same processes. Override instructions for the target processor can be inserted and alternate memory locations jumped to under control of the same debug module, thereby using hardware resources efficiently.