Abstract: A method, structure and system for capacitive sensing is provided. A system includes: a two-dimensional electrode structure, wherein the two-dimensional sensing structure includes a channel for capacitive sensing, at least one integrated circuit connected to the two dimensional sensing structure and configured to mitigate external interference associated with the capacitive sensing by i) receiving a input signal from the two-dimensional electrode structure or ii) providing a select signal to the two-dimensional structure, and a data acquisition device connected to the two-dimensional electrode structure via the integrated circuit configuration and configured to receive an output signal from the integrated circuit.

Abstract: Method, structure and system for capacitive sensing. A system includes: a two-dimensional electrode structure, where the two-dimensional sensing structure includes a channel for capacitive sensing, at least one integrated circuit connected to the two-dimensional electrodestructure and configured to mitigate external interference associated with the capacitive sensing by i) receiving an input signal from the two-dimensional electrode structure or ii) providing a select signal to the two-dimensional structure, and a data acquisition device connected to the two-dimensional electrode structure via the integrated circuit configuration and configured to receive an output signal from the integrated circuit.

Abstract: A method, structure and system for capacitive sensing is provided. The structure includes: one or more first conductive lines arranged in a first arrangement in relation to a first substrate, one or more second conductive lines connected arranged in a second arrangement in relation to a second substrate, one or more first vias embedded on the first substrate and connecting one or more first electrodes to each respective one of the one or more first conductive lines; and one or more second vias embedded on the second substrate and connecting the one or more second electrodes to each respective one of the one or more second conductive lines, where the one or more first conductive electrodes and the second one or more electrodes are parallel and overlapping with respect to one another, and, where i) the first conductive electrodes and ii) the second conductive electrodes form a two-dimensional configuration.

Abstract: A method, structure and system for capacitive sensing is provided. A system includes: a two-dimensional electrode structure, wherein the two-dimensional sensing structure includes a channel for capacitive sensing, at least one integrated circuit connected to the two dimensional sensing structure and configured to mitigate external interference associated with the capacitive sensing by i) receiving a input signal from the two-dimensional electrode structure or ii) providing a select signal to the two-dimensional structure, and a data acquisition device connected to the two-dimensional electrode structure via the integrated circuit configuration and configured to receive an output signal from the integrated circuit.

Abstract: A method, structure and system for capacitive sensing is provided. The structure includes: one or more first conductive lines arranged in a first arrangement in relation to a first substrate, one or more second conductive lines connected arranged in a second arrangement in relation to a second substrate, one or more first vias embedded on the first substrate and connecting one or more first electrodes to each respective one of the one or more first conductive lines; and one or more second vias embedded on the second substrate and connecting the one or more second electrodes to each respective one of the one or more second conductive lines, where the one or more first conductive electrodes and the second one or more electrodes are parallel and overlapping with respect to one another, and, where i) the first conductive electrodes and ii) the second conductive electrodes form a two-dimensional configuration.

Abstract: Method, structure and system for capacitive sensing. A system includes: a two-dimensional electrode structure, where the two-dimensional sensing structure includes a channel for capacitive sensing, at least one integrated circuit connected to the two-dimensional two-dimensional electrodestructure and configured to mitigate external interference associated with the capacitive sensing by i) receiving an input signal from the two-dimensional electrode structure or ii) providing a select signal to the two-dimensional structure, and a data acquisition device connected to the two-dimensional electrode structure via the integrated circuit configuration and configured to receive an output signal from the integrated circuit.

Abstract: LGA connectors are fabricated with buttons or spring contacts preformed to different heights to accommodate the initial topography of a typical module or PCB of a particular product type. This is accomplished during fabrication by measuring topographies of mating surfaces of a first electronic device and of a second electronic device; fabricating interposer contacts to form opposing non-planar sides having respective inverse topographies for contacting the mating surfaces; and sandwiching the interposer between the first and second electronic devices with the opposing sides in contact with respective mating serfaces. For those LGA types made by molding techniques such as the metal-in-polymer type (eg. Tyco Electronics MPI, or Shin Etsu RP) or the Metal-on-Elastomer type (IBM), using molds with the desired topography provides the desired LGA topography.

Abstract: Integrated optoelectronic chips or collections of chips on a module that have both electrical as well as optical interconnects offer many advantages in speed, power consumption and heat generation. Mixed signal types, however, pose significant packaging challenges. This invention describes a land grid array (LGA) interposer which can simultaneously connect electrical and optical signals from a module to a printed circuit board.

Abstract: An active matrix display includes a plurality of pixels arranged in an array, a first transistor and a second transistor associated with each pixel, the first and second transistors positioned within the array for controlling current flow through each pixel, a light emitting diode associated with each pixel; and a storage capacitor associated with each pixel, wherein, during a time period for establishment of a threshold voltage on the storage capacitor for the first transistor, a voltage equal to the sum of the threshold voltage and a voltage for compensating for turnoff of the second transistor is established on the storage. capacitor.