Abstract: The present invention is directed to providing a phase detector capable of establishing phase-locked-loop operation in a highly accurate and reliable manner. For example, exemplary embodiments detect a phase difference between at least two input signals to phase lock the input signals to one another. Exemplary embodiments include two phase detectors each of which receives the two input signals (e.g., three-state phase detectors), and each of which is forced to operate outside of its dead-band region by introducing predetermined phase delays for its inputs. Each of the two phase detectors detects a phase difference between its respective inputs. The two phase differences are then combined to produce a composite output signal formed as a net charge proportional to the net phase difference detected by the two phase detectors.

Abstract: To read the threshold voltage of a transistor such as a floating gate transistor in an analog or multi-level memory cell, the transistor is connected in a feedback loop which contains a differential amplifier having an output terminal and an input terminal respectively connected to the gate and a node (source or drain) of the transistor. A reference voltage is asserted to a second input terminal of the differential amplifier. A load provides a current which charges the node, and the differential amplifier adjusts the gate voltage of the memory cell to an equilibrium value where current through the transistor is equal to current through the reference cell. The equilibrium value of the gate voltage depends on and indicates the threshold voltage of the transistor. In one embodiment of the invention, the load is a current source which mirrors a current through a reference cell that is structurally identical to the transistor, and the drain of the reference cell provides the reference voltage to the amplifier.

Abstract: A read circuit includes a driver which changes a gate voltage of a memory cell and a sense circuit which identifies when the memory cell trips. The driver searches for the threshold voltage of the memory cell using stages which ramp up gate voltage and stages which ramp down the gate voltage. Each stage ends when the sense circuit senses that the memory cell trips, i.e. begins or stops conducting. Initial stages of the search have high ramp rates so that the gate voltage reaches the threshold voltage. These initial stages can give inaccurate threshold voltage readings because high ramp rates change the gate voltage during the period between the transistor tripping and sensing the trip. Later stages ramp the gate voltage slowly to provide an accurate threshold voltage reading. The low ramp rate of the last stage provides accuracy, and the high ramp rate of the initial stages reduces read time. To further reduce read time, the search process can begin at a median voltage for possible threshold voltages.

Abstract: A pro-capture circuit for a phase locked loop detects when the phase locked loop is operating outside of its operating range, and then forces the phase locked loop back into the proper range. The principle of detection is general and may be adapted to work in distinct phase locked loop designs. More particularly, the pro-capture circuit is used in a phase locked loop having a normal operating range in which an output signal of the phase locked loop varies between a minimum normal value and a maximum normal value. The pro-capture circuit includes circuitry for sensing when the output signal is outside the normal operating range and circuitry for forcing the output signal to reenter the normal operating range.

Abstract: A virtual sensing system includes a sensing network that is external to a standard cell for sensing a reference current in the standard cell and for generating a scaled current without breaking the reference current path and without inserting any sensing device in series with the reference current. The reference current can be used, for example, for duplication and/or scaling.