Abstract: A treatment system (100) comprises a process chamber (101) for dynamic or static treatment of at least one substrate. An inductively coupled plasma source, ICP source (120, 120?), comprises at least one inductor (130a, 130b) extending along the longitudinal direction of the ICP source (120, 120?), a gas supply device (141, 142) for one or a plurality of process gases, and a gas directing arrangement (150) disposed in the process chamber (101), said gas directing arrangement (150) extending along the longitudinal direction of the ICP source (120, 120?) and partially surrounding the at least one inductor (130a, 130b).

Abstract: A continuous machine (100) for coating substrates (103) comprises a process module (130) and a vacuum lock (110, 150) for introducing the substrates (103) or removing the substrates (103). The vacuum lock (110, 150) comprises a chamber for receiving a substrate carrier (102) with a plurality of substrates (103) and a flow channel arrangement for evacuating and venting the chamber. The flow channel arrangement comprises a first channel for evacuating and venting the chamber and a second channel for evacuating and venting the chamber, wherein the first channel and the second channel are arranged at opposing sides of the chamber.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.

Abstract: A processor including an instruction fetcher to fetch instructions, a decoder to decode the instructions, at least one load unit adapted to load data, at least one execution unit adapted to perform arithmetic computations on the data by executing the fetched and decoded instructions, a register file adapted to store results of the arithmetic computations, and a multiplexer arrangement provided such that one or more units of the execution unit selectively obtain operands from one of: the register file or a unit used for arithmetic computation of a preceding instruction. The processor is adapted to process and execute the instructions such that processing of the instructions is started under the following conditions: the execution unit is ready for instruction execution, and data from the at least one load unit is available to the at least one execution unit.

Abstract: A method of evaluating a wear state of an assembly of a flow machine, in particular, of a bearing arrangement of a pump or turbine. For determining a wear characteristic, a mechanical query signal having a pre-definable signal shape is generated by a signal generator and a response signal generated from the query signal is detected using a sensor in contact with the assembly. The response signal is varied in dependence on a variation of a physical operating value of the assembly in accordance with a characteristic pattern, the wear characteristic is determined from the variation of the response signal and the wear state is evaluated using the wear characteristic.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. Each processor has a processing element, an input register and an output register, each of which is connected to a segment of the segmented bus system. The segmented bus system provides a plurality of selectable data paths between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the processed results to the external memory.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. Each processor has a processing element, an input register and an output register, each of which is connected to a segment of the segmented bus system. The segmented bus system provides a plurality of selectable data paths between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A method for operating a system on a chip comprising a conventional processor unit (CISC, RISC, VLIW, DSP) and an array processor having a multidimensional arrangement of arithmetic units. Operation information for the array processor are stored in a memory shared between the conventional processor and the array processor. At runtime the conventional processor points the array processor to the memory area comprising the operation information. A management unit inside the array processor is autonomously loading the operation information into the array processor.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory. The method includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the process results external memory.

Abstract: An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A method of evaluating a wear state of an assembly of a flow machine, in particular, of a bearing arrangement of a pump or turbine. For determining a wear characteristic, a mechanical query signal having a pre-definable signal shape is generated by a signal generator and a response signal generated from the query signal is detected using a sensor in contact with the assembly. The response signal is varied in dependence on a variation of a physical operating value of the assembly in accordance with a characteristic pattern, the wear characteristic is determined from the variation of the response signal and the wear state is evaluated using the wear characteristic.