Abstract: A printed circuit board includes a power plane and a ground reference plane that includes two opposite sides. The power plane is positioned proximate one side of the ground reference plane. A signal layer is positioned proximate the other side of the ground reference plane to isolate the power plane from the signal layer. Any noise on the power plane or the signal layer is thus isolated by the intervening ground plane.

Abstract: A discontinuity, such as a via, in a signal transmission line can introduce a parasitic element that affects the signal transmission. The method in accordance with embodiments of the present invention are directed to counteracting the transmission line parasitic element discontinuity. The method includes determining the amount of parasitic capacitance or inductance that is introduced at a portion of the transmission line, such as by the via. A suitable amount of delay is introduced to the transmission line by way of correction impedance in order to counteract the affects of the parasitic element. The delay is calculated taking into account at least in part the correction impedance and the parasitic element effect. The correction impedance is suitably added to a portion of the transmission line at which the parasitic element is present.

Abstract: A method for manufacturing a bus having enhanced signals qualities which includes the steps of determining the intrinsic inductance per unit length (L.sub.0) and intrinsic capacitance per unit length (C.sub.0) of the unloaded bus. The method also includes the step of determining the load capacitance per unit length (C.sub.d) of the bus that is attributable to the peripheral devices that will be attached to the bus. Based on these values, an adjustment inductance (L.sub.d) per unit length for the bus is calculated for the bus with L.sub.d being substantially equal to L.sub.0 * C.sub.d /C.sub.0. Finally, one inductor of value L.sub.d is added per unit length of the bus. The added adjustment inductance offsets the capacitance attributable to the peripheral devices attached to the bus. The result is that signals within the bus have rise and fall times acceptable for high speed operation.

Abstract: To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.

Abstract: A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A multilayer pressure stack (microstack) has a plurality of layers formed of a material that may have a high time-dependent deformation factor and a plurality of segments formed in each layer. Each segment comprises a conductive material having a low time-dependent deformation factor and pressure is provided along a column of aligned segments to establish electrical interconnections between the segments in various layers. Interposers formed of non-conductive material may be provided in selected segments to form points of electrical isolation. The plurality of layers, or wafers, includes signal wafers and ground/voltage wafers. The signal wafers are formed of a low dielectric constant material to optimize the propagation velocity of signals traveling in signal traces connecting selected segments in the signal wafer. More than 100 wafers may be provided in a microstack and repairs and revisions of conductor routing are easily accomplished by substituting new wafers within the microstack.