Patents by Inventor Frank Minardi

Frank Minardi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040106279
    Abstract: A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.
    Type: Application
    Filed: November 12, 2003
    Publication date: June 3, 2004
    Inventors: Steven Mark Anderson, Siddhartha Bhowmik, Joseph William Buckfeller, Sailesh Mansinh Merchant, Frank Minardi
  • Patent number: 6720261
    Abstract: A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: April 13, 2004
    Assignee: Agere Systems Inc.
    Inventors: Steven Mark Anderson, Siddhartha Bhowmik, Joseph William Buckfeller, Sailesh Mansinh Merchant, Frank Minardi
  • Patent number: 6699372
    Abstract: The present invention provides a method of depositing a film on a surface of a coil that includes depositing a metal from a target onto a surface of a coil to form a first film on the surface and forming a second film over the first film at a low pressure and at a first power at the target that is substantially higher than a first power at the component's surface. The conditioned deposition tool is well suited for manufacturing integrated circuits.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: March 2, 2004
    Assignee: Agere Systems Guardian Corporation
    Inventors: Siddhartha Bhowmik, Sailesh M. Merchant, Frank Minardi
  • Publication number: 20020189932
    Abstract: The present invention provides a method of depositing a film on a surface of a coil that includes depositing a metal from a target onto a surface of a coil to form a first film on the surface and forming a second film over the first film at a low pressure and at a first power at the target that is substantially higher than a first power at the component's surface. The conditioned deposition tool is well suited for manufacturing integrated circuits.
    Type: Application
    Filed: April 16, 2001
    Publication date: December 19, 2002
    Inventors: Siddhartha Bhowmik, Sailesh M. Merchant, Frank Minardi