Abstract: Embodiments relate to an inter-processor memory. An aspect includes a plurality of memory banks, each of the plurality of memory banks comprising a respective plurality of parallel memory modules, wherein a number of the plurality of memory banks is equal to a number of read ports of the inter-processor memory, and a number of parallel memory modules within a memory bank is equal to a number of write ports of the inter-processor memory. Another aspect includes each memory bank corresponding to a single respective read port of the inter-processor memory, and wherein, within each memory bank, each memory module of the plurality of parallel memory modules is writable in parallel by a single respective write port of the inter-processor memory.

Abstract: A method for scheduling a plurality of resources for processing a plurality of requests is provided. The method sorts the requests, each specifying a priority and one or more resources that process the request, in parallel based on the priorities. The method initializes an output set to an empty set and filters out any request that has a resource conflict with a current highest priority request, adds the current highest priority request to the output set and determines whether one or more requests of the plurality of requests, other than the requests added to the output set, are not filtered out. Responsive to determining that the one or more requests are not filtered out, repeating filtering, adding, and determining by using a highest priority request of the one or more requests as a current highest priority request. The method causes the assigned resources to process the output set of requests in parallel.

Abstract: Embodiments relate to an inter-processor memory. An aspect includes a plurality of memory banks, each of the plurality of memory banks comprising a respective plurality of parallel memory modules, wherein a number of the plurality of memory banks is equal to a number of read ports of the inter-processor memory, and a number of parallel memory modules within a memory bank is equal to a number of write ports of the inter-processor memory. Another aspect includes each memory bank corresponding to a single respective read port of the inter-processor memory, and wherein, within each memory bank, each memory module of the plurality of parallel memory modules is writable in parallel by a single respective write port of the inter-processor memory.

Abstract: An imaging system disables pixel integration for images within frames that are identified as moving while enables pixel integration for images that are not moving. The system may implement a frame-averaging type of integration or recursive types of frame integration, or may refrain from performing frame integration. On a pixel-by-pixel basis, the system may compare a pixel from frame memory with a corresponding pixel of an input frame and may disable pixel integration for the pixel when a difference between the compared pixels exceeds a threshold. One of the integration processes may be performed on the pixels when the difference does not exceed the threshold. When frame integration is disabled or de-selected (e.g., for pixels having motion), the frame memory may be bypassed and a self-integration may be performed with corresponding pixels from a current frame effectively resulting in no integration.

Abstract: A system (100) and method for outputting data from a detector (104). The novel system (100) includes a first controller (118) that samples the detector (104) at a first rate, a memory (112) for storing the sampled data, and a second controller (120) that outputs data from the memory (112) at a second rate. In a illustrative embodiment, the first rate is symmetrical from field to field, while the second rate is asymmetrical from field to field.

Abstract: An imaging system disables pixel integration for images within frames that are identified as moving while enables pixel integration for images that are not moving. The system may implement a frame-averaging type of integration or recursive types of frame integration, or may refrain from performing frame integration. On a pixel-by-pixel basis, the system may compare a pixel from frame memory with a corresponding pixel of an input frame and may disable pixel integration for the pixel when a difference between the compared pixels exceeds a threshold. One of the integration processes may be performed on the pixels when the difference does not exceed the threshold. When frame integration is disabled or de-selected (e.g., for pixels having motion), the frame memory may be bypassed and a self-integration may be performed with corresponding pixels from a current frame effectively resulting in no integration.

Abstract: A system (100) and method for outputting data from a detector (104). The novel system (100) includes a first controller (118) that samples the detector (104) at a first rate, a memory (112) for storing the sampled data, and a second controller (120) that outputs data from the memory (112) at a second rate. In a illustrative embodiment, the first rate is symmetrical from field to field, while the second rate is asymmetrical from field to field.

Abstract: An analog signal processor for use with an array of uncooled detectors. Each detector has an amplifier associated therewith and each amplifier provides gain. A first circuit (212, 294, 300, 220) is included for compensating for a DC offset of each detector/amplifier pair of the array. A second circuit (250, 294, 300) corrects for variations in the sensitivity of each detector/amplifier pair. As a result, the outputs each of the detector/amplifier pairs in response to a common input signal are equalized. In a specific implementation, additional circuits are included providing global automatic DC level control across the array (270, 280, 294, 300), global automatic gain control across the array (250, 262, 294, 300) and frame-to-frame offset adjustment (212, 230).

Abstract: A digital signal processing system (100) removes DC bias in the output of a pyroelectric detector and similar types of detectors by adding together a first output signal which is inverted and a second output signal which is not inverted. The system (100) also removes offsets in the detector signal introduced by electronic circuits (readouts, amplifiers, drivers, etc.) between the detector and the system (100).