Patents by Inventor Frank N. Cornett
Frank N. Cornett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10116413Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.Type: GrantFiled: August 22, 2017Date of Patent: October 30, 2018Assignee: Intel CorporationInventors: Frank N. Cornett, Brent R. Rothermel
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Patent number: 9948507Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.Type: GrantFiled: July 28, 2016Date of Patent: April 17, 2018Assignee: INTEL CORPORATIONInventors: Frank N. Cornett, Brent R. Rothermel
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Publication number: 20170353266Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Applicant: Intel CorporationInventors: Frank N. Cornett, Brent R. Rothermel
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Patent number: 9742523Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.Type: GrantFiled: November 29, 2016Date of Patent: August 22, 2017Assignee: INTEL CORPORATIONInventors: Frank N. Cornett, Brent R. Rothermel
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Publication number: 20170085337Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.Type: ApplicationFiled: November 29, 2016Publication date: March 23, 2017Applicant: Intel CorporationInventors: Frank N. Cornett, Brent R. Rothermel
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Patent number: 9509438Abstract: One embodiment provides a network controller having physical interface (PHY) circuitry that includes transmitter circuitry configured to transmit data frames to a link partner over a channel link. The network controller also includes a link speed cycling module configured to cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period allows the link partner to lock on to the transmitted data frames.Type: GrantFiled: December 27, 2013Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: Frank N. Cornett, Brent R. Rothermel
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Publication number: 20160337183Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicant: Intel CorporationInventors: FRANK N. CORNETT, BRENT R. ROTHERMEL
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Patent number: 9432229Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.Type: GrantFiled: June 29, 2015Date of Patent: August 30, 2016Assignee: Intel CorporationInventors: Frank N. Cornett, Brent R. Rothermel
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Publication number: 20150304142Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.Type: ApplicationFiled: June 29, 2015Publication date: October 22, 2015Applicant: INTEL CORPORATIONInventors: Frank N. Cornett, Brent R. Rothermel
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Patent number: 9106467Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.Type: GrantFiled: November 8, 2013Date of Patent: August 11, 2015Assignee: Intel CorporationInventors: Frank N. Cornett, Brent R. Rothermel
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Publication number: 20150131708Abstract: One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Inventors: Frank N. Cornett, Brent R. Rothermel
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Publication number: 20150092791Abstract: One embodiment provides a network controller. The network controller includes physical interface (PHY) circuitry comprising transmitter circuitry configured to transmit data frames to a link partner in communication with the transmit circuitry over a channel link. The network controller also includes a link speed cycling module configured to, upon initialization of the PHY circuitry, cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed.Type: ApplicationFiled: December 27, 2013Publication date: April 2, 2015Inventors: FRANK N. CORNETT, BRENT R. ROTHERMEL
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Patent number: 8031823Abstract: A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.Type: GrantFiled: October 7, 2008Date of Patent: October 4, 2011Assignee: Silicon Graphics, Inc.Inventors: Philip Nord Jenkins, Frank N. Cornett
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Publication number: 20090034673Abstract: A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.Type: ApplicationFiled: October 7, 2008Publication date: February 5, 2009Applicant: Silicon Graphics, Inc.Inventors: Philip Nord Jenkins, Frank N. Cornett
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Patent number: 7433441Abstract: A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.Type: GrantFiled: April 17, 2006Date of Patent: October 7, 2008Assignee: Silicon Graphics, Inc.Inventors: Philip Nord Jenkins, Frank N. Cornett
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Patent number: 7248635Abstract: The present invention is directed toward a communications channel comprising a link level protocol, a driver, a receiver, and a canceller/equalizer. The link level protocol provides logic for DC-free signal encoding and recovery as well as supporting many features including CRC error detection and message resend to accommodate infrequent bit errors across the medium. The canceller/equalizer provides equalization for destabilized data signals and also provides simultaneous bi-directional data transfer. The receiver provides bit deskewing by removing synchronization error, or skewing, between data signals. The driver provides impedance controlling by monitoring the characteristics of the communications medium, like voltage or temperature, and providing a matching output impedance in the signal driver so that fewer distortions occur while the data travels across the communications medium.Type: GrantFiled: July 20, 2000Date of Patent: July 24, 2007Assignee: Silicon Graphics, Inc.Inventors: Michael R. Arneson, Terrance L. Bowman, Frank N. Cornett, John F. DeRyckere, Brian T. Hillert, Philip N. Jenkins, Nan Ma, Joseph M. Placek, Rodney Ruesch, Gregory M. Thorson
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Patent number: 7031420Abstract: A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. Each of the plurality of delayed signals is compared to a reference signal to detect changes in the skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in the detected skew.Type: GrantFiled: December 30, 1999Date of Patent: April 18, 2006Assignee: Silicon Graphics, Inc.Inventors: Philip Nord Jenkins, Frank N. Cornett
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Patent number: 6831924Abstract: A variable communication systems comprising a plurality of transceivers and a control circuit connected to the transceivers to configure the transceivers to operate in a bi-directional mode and a uni-directional mode at different times using different transfer methods to transfer data.Type: GrantFiled: July 20, 2000Date of Patent: December 14, 2004Assignee: Silicon Graphics, Inc.Inventors: Frank N. Cornett, Philip N. Jenkins, Terrance L. Bowman, Joseph M. Placek, Gregory M. Thorson
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Patent number: 4825173Abstract: An amplifier includes a first differential pair of transistors with commonly connected input electrodes also connected to a variable current sink. A common mode voltage control circuit includes a second differential pair of transistors, one of which has a control electrode coupled to the output electrodes of the first differential pair. The second differential pair provides control signals to the variable current sink to regulate the common mode output voltage. Current control circuitry is coupled to the variable current sink to allow adjustment of the gain, bandwith or power dissipation of the first differential pair.Type: GrantFiled: January 18, 1988Date of Patent: April 25, 1989Assignee: Motorola, Inc.Inventor: Frank N. Cornett
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Patent number: 4768208Abstract: A timing error estimator which samples a received stream of data symbols at the beginning, end, and a mid-point of a symbol period is disclosed. These samples are used with a model that assumes that a data stream waveform should transition along a straight line between its values at optimum sampling instances, separated by the symbol period. Differences between a mid-symbol sample estimated using this straight line model and the actual mid-symbol sample are assumed to be due to a timing error. The timing error estimator preforms computations on complex inputs and therefore is compatible with a wide variety of modulation types.Type: GrantFiled: March 9, 1987Date of Patent: August 30, 1988Assignee: Motorola, Inc.Inventor: Frank N. Cornett